US 4,225,959 A · Tri-state bussing system

Abstract

This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system. The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the data group in the error correcting apparatus, the operation in progress is aborted if an error has been detected, and the error is not correctable. If correctable, the correct instruction data group is applied to the execution unit. If no error is detected in the data group, utilization of the data group proceeds uninterrupted. Two, three state busses are employed. The first three state bus is used to transmit memory data to the error detection and correction (EDAC) circuitry, to transmit corrected data from the (EDAC) circuitry and to the data output circuits and to transmit input data to the memory. The second three-state bus transmits data to the instruction buffer, to the EDAC circuitry and also transmits corrected data from data output circuits to the instruction buffer.

Claims10

Dependent claims

A bussing apparatus within a data processing system central processor including a memory capable of storing data groups, said apparatus supplying an accurate data group to an instruction buffer comprising:

a first data bus receiving a data group from said memory and coupled to said instruction buffer for supplying said data group thereto;
a first means connected to said first data bus for transferring said data group;
a data register storing said data group from said first means;
a second data bus connected to said first means for supplying said data group to said data register;
an error detection and correction circuitry connected to receive said data group from said data register and producing a corrected data group;
a second means transferring said corrected data group to said second data bus;
a third means connected to transfer said corrected data group from said second data bus to said first data bus whereby said corrected data group is supplied to said instruction buffer from said first data bus.

4 more elements

Dependencies are inferred from the claim text.

Tri-state bussing system

Life of this patent

Tri-state bussing system

Life of this patent

Abstract

Claims10