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US 4,225,958 AGranted
Device comprising circuits for holding, in particular, a test data signal
AssigneeVLSI Technology Research Association
InventorShigehiro Funatsu
Life of this patent
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AssigneeVLSI Technology Research Association
InventorShigehiro Funatsu
Estimating the term…
An electronic device, such as an LSI, comprising a logic circuit and an electronic circuit that comprises, in turn, a large-capacity memory circuit and/or at least one oscillator is provided with a holding circuit between the logic and the electronic circuits and between the electronic circuit and a device output terminal. The holding circuit merely delivers output signals of the logic circuit to the electronic circuit and feeds back output signals of the electronic circuit to the logic circuit in normal operation of the device. During test of the logic and the electronic circuits, the holding circuit selects and holds a test signal of a preselected time-sequential pattern and is switched to select the logic circuit output signals, which are produced by the device with a prescribed combination of logic levels when the device has no defects. Similarly, a holding circuit output signal is given a predetermined time-sequential pattern. Preferably, the holding circuit comprises first and second holding circuits equal in number to inputs and outputs, respectively, of the electronic circuit to serve as mere data buses and a shift register in the normal and the test modes of operation, respectively.
An electronic device operable in either of a normal and a test mode and comprising a first input terminal for receiving a first data signal in whichever of said normal and said test modes, a second input terminal for receiving a second data signal in said test mode, an output terminal, a logic circuit for receiving said first and said second data signals from said first and said second input terminals, respectively, an electronic circuit, and holding means between said logic and said electronic circuits and between said electronic circuit and said output terminal, said holding means being responsive in said normal mode to said first data signal for supplying a third data signal to said output terminal in cooperation with said logic and said electronic circuits and for selectively holding said first and said second data signals only in said test mode to supply a fourth data signal to said output terminal in cooperation with said logic and said electronic circuits.
A holding circuit operable in either of a normal and a test mode and responsive to a first data input signal in whichever of said normal and said test modes, a second data input signal in said test mode, a first control signal having a first level in said normal mode and either of said first level and a second level in said test mode, and a second control signal having a third and a fourth level in said normal and said test modes, respectively, which comprises:
Dependencies are inferred from the claim text.