Controller for bubble memories

An apparatus for selectively transferring data to and from an m-row utilization array, said array having known positions from which data is to be excluded, data being transferrable to and from said array in parallel via an m-bit port, successive columns of said array being accessible upon occurrence of array access signals, comprising:

• first parallel register means, connected to said m-bit port, for transferring data in parallel to or from said array upon occurrence of an array access signal;
• control means, responsive to signals indicative of said known positions, for selectively transferring data to or from locations of said first parallel register means corresponding to positions in an accessible array column from which data is not to be excluded,
• valid data memory means, cooperating with said control means, for storing said signals indicative of known positions in said utilization array from which data is to be excluded, said memory means being accessed in relation to occurrence of said array access signals and supplying said position indicative signals to said control means,
• a second parallel register means, connectable to an n-bit input/output data port,
• said control means comprising circuitry, interconnecting said first and second parallel register means, for transferring data therebetween in serial form, said circuitry being configured to inhibit such transfer of data to or from locations in said first parallel register means specified by said position indicative signals accessed from said memory means, and having;
• another like first parallel register means and another like second parallel register means, and wherein;
• said utilization array is connected to said first parallel register means via a "read data" bus and a second utilization array is connected to said other first parallel register means via a "write data" bus,
• said control means circuitry further interconnecting said other first and other second parallel register means, the contents of said valid data memory means being utilized by said control means circuitry to selectively transfer data between said first and second parallel register means and between said other first and other second parallel register means.

An apparatus for selectively transferring data to and from an m-row utilization array, said array having known positions from which data is to be excluded, data being transferrable to and from said array in parallel via an m-bit port, successive columns of said array being accessible upon occurrence of array access signals, comprising:

• first parallel register means, connected to said m-bit port, for transferring data in parallel to or from said array upon occurrence of an array access signal;
• control means, responsive to signals indicative of said known positions, for selectively transferring data to or from locations of said first parallel register means corresponding to positions in an accessible array column from which data is not to be excluded,
• a plurality of second parallel register means, each connectable to a corresponding parallel data port of arbitrary width, and
• steering data supply means, cooperating with said control means, for supplying said position indicative signals, said signals further indicating which of said corresponding parallel data ports is to be the source or destination of data from each position in said accessible array column from which data is not to be excluded,
• said control means comprising circuitry, interconnecting said first parallel register means and said plurality of second parallel register means, for selectively transferring data bits in serial between said first parallel register means and specific ones of said second parallel register means in accordance with the position indicative signals supplied from said steering data supply means.

An apparatus for controlling the transfer of data between an m-bit parallel external data bus and a plurality n of bubble memories some of which contain defective storage sites at which data cannot be stored, said apparatus comprising:

• a first shift register having n storage locations, each storage location connected to one corresponding bubble memory for parallel data transfer between said bubble memories and said first shift register,
• a second shift register having m storage locations connectable to said external data bus for parallel data transfer therebetween,
• serial interconnection means for serially transferring data between said first and second shift registers,
• a "valid data" memory storing signals identifying the locations of said bubble memory defective storage sites,
• shift control means, cooperating with said "valid data" memory and with said serial interconnection means, for causing data to be transferred between said first and second shift registers only to or from storage locations in said first shift register associated with accessible non-defective bubble memory storage sites identified by signals accessed from said "valid data" memory, said shift control means further comprising:
• a shift clock generation circuit, generating a first series of shift pulses, connected to said first shift register to cause the serial shifting of data in or out thereof, and
• "valid data" shift control logic, cooperating with said "valid data" memory and with said shift clock generation circuit, providing "valid data" shift pulses to said second shift register, each "valid data" shift pulse being in synchronism with one of said first series of shift pulses but occurring only when said data being transferred to or from said second shift register originated from or is destined for a non-defective bubble memory storage position,
• said second shift register being connected to an external originator or user of data via said m-bit parallel external data bus,
• load control circuitry, cooperating with said "valid data" shift control logic, for enabling the parallel loading of data from said second shift register to said external data bus or from said external data bus to said second shift register upon occurrence of each group of m "valid data" shift pulses, and wherein;
• said external data bus includes associated control lines including:
• a transfer request line for requesting of the originator or user of data to perform a data transfer via said external bus, and
• a transfer knowledge line, controlled by said data originator or user, for acknowledgement of such transfer after occurrence of a request via said request line, together with:
• request control circuitry, cooperating with said load control circuitry and with said transfer request and acknowledge lines, for coordinating the loading of data from or to said second shift register with occurrence of request and acknowledgement signals from said request and acknowledge lines.

An apparatus for controlling the transfer of data between an m-bit parallel external data bus and a plurality n of bubble memories some of which contain defective storage sites at which data cannot be stored, said apparatus comprising:

• a first shift register having n storage locations, each storage location connected to one corresponding bubble memory for parallel data transfer between said bubble memories and said first shift register,
• a second shift register having m storage locations connectable to said external data bus for parallel data transfer therebetween,
• serial interconnection means for serially transferring data between said first and second shift registers,
• a "valid data" memory storing signals identifying the locations of said bubble memory defective storage sites,
• shift control means, cooperating with said "valid data" memory and with said serial interconnection means, for causing data to be transferred between said first and second shift registers only to or from storage locations in said first shift register associated with accessible non-defective bubble memory storage sites identified by signals accessed from said "valid data" memory,
• said apparatus connecting to an external originator or user of data via said m-bit parallel external data bus, and further comprising:
• a transfer request line for requesting the originator or user of data to perform a data transfer via said data signal lines,
• a transfer acknowledge line, controlled by said data originator or user, for acknowledgment of the occurrence of a data transfer after such transfer was requested by use of said transfer request line,
• a "valid data" pulse circuit, a constituent of said shift control means, connected to said second shift register and able to cause the shifting of said second shift register by the generation of "valid data" shift pulses, each said "valid data" shift pulse occurring only when data to be transferred between said first shift register and said second shift register is destined for or originated from a non-defective bubble memory storage site, and
• a second shift register counter circuit, connected to receive "valid data" shift pulses from said "valid data" pulse circuit, said counter circuit having an output signal line and a reset signal line, said output signal line being pulsed for each m "valid data" shift pulses, said output signal line being connected to and controlling said transfer request line, said transfer acknowledge line being connected to said reset signal line to cause the clearing of said counter circuit.