Command queue apparatus included within a cache unit for facilitating command sequencing

A cache unit for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled through a system interface to said cache unit in response to commands received from said data processing unit, said cache unit comprising:

• a plurality of command buffer means, each coupled to said system interface and each comprising a number of addressable locations, one command buffer means for storing a number of words of each first type of command to be transferred to said system interface and another command buffer means for storing each second type of command;
• command queue means coupled to each of said buffer means, said command queue means comprising a plurality of addressable multibit locations corresponding in number to the sum of said number of locations within said each of said command buffer means;
• and,
• control means coupled to said command queue means and to each of said buffer means, said control means being operative in response to a first word, each command of said first and second types to generate signals for writing a first entry into a next available one of said multibit locations, said first entry being coded to include predetermined characteristics of said command being loaded into a next available one of said locations of one of said command buffer means and said control means being operative upon the read out of said first entry to generate signals for transferring said words of said command to said system interface and the loading of a new command within said one buffer when there are a number of locations available to accommodate a predetermined first type of command.

A cache system for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled through a system interface to said cache system in response to commands received from said data processing unit, each write type command including a command word and a number of data words, said cache system comprising:

• a first register coupled to said system interface for transferring said command word of each write type command;
• a second register coupled to said system interface for transferring said data words of each write type command;
• an addressable write command buffer coupled to said first and second registers and to said data processing unit, said write command buffer including a plurality of locations for storing said command and data words of said each write type command to be transferred to said system interface;
• and addressable command queue coupled to said write command buffer, said command queue including a plurality of multibit locations;
• and,
• control means coupled to said command queue, said processing unit, said first and second registers and to said write buffer, said control means being operative in response to each command word to generate signals for writing an entry having a predetermined format into a next available one of said plurality of multibit locations, a first one of said entry being coded to identify the type and number of words in addition to the location within said write buffer into which said command word is to be loaded and said control means in response to said entry read out from said command queue being operative to generate signals to transfer said command word to said first register, a first data word to said second register and the loading of a new command into said write buffer in accordance with the progress of said transfer upon detecting the availability of a predetermined number of locations therein.