Operator independent template control architecture
AssigneeBurroughs Corporation
InventorRichard A. Stokes
Life of this patent
Estimating the term…
Abstract
In a microprogrammed data processing pipeline system comprising a plurality of stages, microinstructions for controlling the stages are stored as templates in an addressable template micromemory store and are provided automatically and sequentially to the stages of the pipeline system. Operation microcode is introduced for a particular stage after the templates are issued from the micromemory store but before provision thereof to the pipeline system, thereby allowing a single template to control a plurality of different operations of a particular stage within the pipeline system. Provision is also made to freeze or inhibit the issuance of subsequent templates during the execution of excessively long operations in the particular stage.
Claims5
An operator independent template control architecture for providing microinstructions to a plurality of stages and operation microcode to a particular stage in a microprogrammable pipelined data processing system, said architecture comprising:
- micromemory structure means storing a plurality of microinstructions, said micromemory structure means for providing a microinstruction to each stage in said plurality of stages in said microprogrammable pipelined data processing system, said providing being sequenced with data flow therethrough, said micromemory structure means also storing operation code selection data;
- template parameter store means storing a plurality of operation codes for a particular stage in said plurality of stages;
- selection means fed by said template store means and controlled by operation code selection data from said micromemory structure means, said selection means selecting a particular one of said plurality of operation codes;
- translation means fed by said selection means for translating said selected particular one of said plurality of operation codes into a operation microcode for specifying an operation to be executed in said particular stage in said plurality of stages in said microprogrammable pipelined data processing system;
- and coordination means receiving said microinstruction for each stage from said micromemory structure means and said operation microcode from said translation means, said coordination means for providing said operation microcode to said particular stage in said plurality of stages coincident with the providing of a microinstruction thereto by said micromemory structure means.
Dependencies are inferred from the claim text.