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US 4,225,849 AGranted
N-Bit magnitude comparator of free design
AssigneeFujitsu Limited
InventorHung C. Lai
Life of this patent
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Abstract
An N-bit magnitude comparator of tree design having a plurality of one-bit magnitude comparators connected to a cascading network with a first stage adapted to receive signals from each pair of the one-bit magnitude comparators and subsequent stages for receiving signals from the preceding stage in the cascade network. The first and every alternate stage thereafter in the cascading circuit comprises means for inverting the signal polarity to the input of that stage so as to achieve one gate delay per circuit.
Claims10
An N-bit magnitude comparator of tree design comprising:
- a magnitude comparator stage for receiving a pair of binary words each binary word comprised of "N" bits, the magnitude comparator state including "N" one-bit magnitude comparator circuits, each of said one-bit magnitude comparator circuits adapted to receive a bit of the same order of each binary word and providing one of three distinct output signals indicative of which of the input bits of the binary words is largest in magnitude or whether the input bits of the binary words are of equal magnitude;
- and
- a first cascade stage comprising N/2 individual cascading circuits with each of said individual cascading circuits connected to receive the output of two of said one-bit magnitude comparator circuits, each of said individual cascading circuits having one-gate delay and providing output signals indicative of which of the output signals from the associated one-bit magnitude comparators is largest in magnitude or whether the input signals are of equal magnitude, the relative polarity of the output being inverted relative to the polarity of the output of the magnitude comparators.
An N-bit magnitude comparator of tree design comprising:
- means for receiving two sets of N-bit binary input signals wherein N is a whole number;
- a one-bit comparator stage including N sets of one-bit comparator circuits with each one-bit comparator circuit adapted for receiving a pair of equal significant bit signals of the binary input;
- a first stage of individual cascading circuits with each individual cascading circuit connected to two sets of one-bit magnitude comparator circuits, each of said individual cascading circuits of said first stage including a two-input, two-wide AND-OR-INVERTER gate and a NOR gate;
- a second stage of cascading circuits for connecting with each of two cascading circuits of said first stage, each of said individual cascading circuits of said second stage including a two-input, two-wide AND-OR-INVERTER gate and a NAND gate;
- and
- a third stage of at least one cascading circuit for connecting with each of two cascading circuits of said second stage, and third stage cascading circuit including a two-input, two-wide AND-OR-INVERTER gate and a NOR gate.
3 more elements
Dependencies are inferred from the claim text.