Coincidence circuit for a protective relay circuit

In a protective relay circuit of the type employing a timer circuit and, a coincidence circuit for receiving a plurality of a.c. input signals and developing a coincidence output signal representative of the phase coincidence of the plurality of a.c. input signals, which coincidence circuit comprises:

• (a) negative signal processing means including:
• (i) first level detector circuit means for developing a separate first level detector output signal for each one of said plurality of a.c. input signals when each one of said plurality a.c. input signals is of a negative value greater than a predetermined negative threshold value, said predetermined negative threshold value being of a different value for at least some of said a.c. input signals,
• (ii) first AND circuit means for receiving said first level detector output signals and developing a first AND output signal representative of negative phase coincidence of said plurality of a.c. input signals wherein said plurality of a.c. input signals are each of a negative value greater than said predetermined negative threshold values,
• (b) positive signal processing means including:
• (i) second level detector circuit means for developing a separate second level detector output signal for each one of said plurality of a.c. input signals when each one of said plurality of a.c. input signals is of a positive value greater than a predetermined positive threshold value, said predetermined positive threshold value being of a different value for at least some of said a.c. input signals,
• (ii) second AND circuit means for receiving said second level detector output signals and developing a second AND output signal representative of positive phase coincidence of said plurality of a.c. input signals wherein said plurality of a.c. input signals are each of a positive value greater than said predetermined positive threshold values, and
• (c) OR circuit means coupled to receive said first and second AND output signals for developing an OR circuit output signal in response to said first or second AND output signal, said OR circuit output signal being representative of the phase coincidence of said plurality of a.c. input signals wherein said predetermined negative and positive threshold values are exceeded for the respective negative and positive portions of said a.c. input signals, said OR circuit output signal being coupled to a timer circuit which measures the duration of said OR circuit output signal and develops an output signal when the phase coincidence occurs for a predetermined minimum time.