US 4,224,734 A · Low electrical and thermal impedance semiconductor component and method of manufacture

Abstract

A semiconductor component and a method for manufacturing the semiconductor component with low electrical and thermal impedances is provided. The semiconductor component includes a thin semiconductor device with a plurality of layers of various conductivity types forming the active regions and semiconductor/metallic transition layers. The low electrical impedance of the component is achieved by the use of the thin semiconductor device, while the low thermal impedance is provided by a thick pedestal metalization on the semiconductor device. The method for manufacturing such a device includes the fabrication of at least one semiconductor device on one surface of a semiconductor substrate. The second surface of the semiconductor substrate is selectively etched by a controlled process to form a cavity of limited lateral extent adjacent to each of the semiconductor devices on the one surface. The surfaces of the device and the second surface of the substrate are selectively metalized such that the second surface metalization fills each of the cavities. Thus, after the individual semiconductor components are separated from each other, the thick metalization in the cavities forms a thick pedestal heat sink of the semiconductor component.

Claims6

Dependent claims

A method of producing at least one low electrical and thermal impedance semiconductor component from a semiconductor substrate with a selected crystalline orientation whose bulk is a first conductivity type, said substrate having a first surface and a second surface, the method comprising the steps of:

fabricating at least one semiconductor device on the first surface of the semiconductor substrate;
controllably etching the second surface of the substrate to thin the cross-section of the selected location for each semiconductor device by forming a cavity of limited lateral extent adjacent to the selected location of each of the semiconductor devices on the first surface of the substrate, the etching continuing along the crystalline planes with the shape of the cavity being defined by the selected crystalline orientation of the substrate;
selectively metalizing the first surface of the substrate after the fabricating step has been completed;
metalizing the second surface, and the interior of the cavities therein, with a metallic layer that is at least as thick as those portions of the substrate surrounding each cavity to overfill each of the cavities;
and
lapping and polishing the second surface of the substrate to remove the metalization from, and to expose those areas of the substrate that surround each cavity and to thin the metalization within each cavity to a selected uniform thickness that is substantially thicker than the cross-section of the substrate in the location of the semiconductor devices.

3 more elements

fabricating at least one semiconductor device on the first surface of the semiconductor substrate;
controllably etching the second surface of the substrate to thin the cross-section of the selected location for each semiconductor device by forming a cavity of limited lateral extent adjacent to the selected location of each of the semiconductor devices on the first surface of the substrate, the etching continuing along the crystalline planes with the shape of the cavity being defined by the selected crystalline orientation of the substrate;
selectively metalizing the first and second surface and the interior surfaces of the cavities within the second surface following the etching step, said second surface metallic layer being at least as thick as those portions of the substrate surrounding each cavity to overfill each of the cavities;
and
lapping and polishing the second surface of the substrate to remove the metalization from, and to expose those areas of the substrate that surround each cavity and to thin the metalization within each cavity to a selected uniform thickness that is substantially thicker than the cross-section of the substrate in the location of the semiconductor devices.

2 more elements

Dependencies are inferred from the claim text.

Low electrical and thermal impedance semiconductor component and method of manufacture

Life of this patent

Low electrical and thermal impedance semiconductor component and method of manufacture

Life of this patent

Abstract

Claims6