Distributed multiprocessor communication system

In a distributed multiprocessor system wherein a plurality of processor modules are distributed along a communication link by way of which the transfer of information from one processor module to another may take place, a method of controlling the transmission and reception of information conveyed by way of said communication link between processor modules, comprising the steps of:

• assigning prescribed address codes to each of the processor modules in said system;
• generating said address codes in each of the processor modules during respective intervals of time;
• for each respective processor module from which the transmission of information to another processor module is to take place, transmitting a message character over said communication link only during an interval of time when the generated address code corresponds to the address code assigned for said each respective processor module, said message character containing the address code of the processor module for whom the message character is intended and a priority code defining the priority level of the message character;
• at said each respective processor module, monitoring said communication link for message characters and causing data included in a message character which contains the address of said each respective processor to be stored in that processor module and
• altering the priority level of all subsequent message characters which will be accepted from the transmitting processor module upon receiving the first message character.

A distributed multi-data processor system wherein a plurality of processor modules, each of which contains a data processing unit, are distributed along a communication link by way of which the transfer of information from one processor module to another processor module is effected, characterized in that each processor module includes:

• transmission means, coupled to said communication link, for transmitting a message character including a priority mode indicator to another processor module in the system and,
• receiver means, coupled to said communication link, for monitoring said communication link for messages transmitted thereover, and for accepting only a message addressed to that particular module,
• means for storing a prescribed code unique to that module and defining the address of the module corresponding to a time interval during which said transmission means may be enabled to transmit a message character to another processor module,
• means, coupled to said storing means and to said transmission means, for repetitively generating a code sequence containing each of the prescribed codes which define the addresses of the respective processor modules of the system,
• comparison means, coupled to said code sequence generating means and said storing means, for enabling said transmission means to transmit a message character upon the output of said code sequence generating means corresponding to the code stored in said storing means, and
• means responsive to the transmission of said priority mode indicator for limiting the transmission of additional message characters to the one processor upon the subsequent generation of the code sequence defining the address of the one processor.

A distributed multi-data processor system wherein a plurality of data processor modules, each of which contains a data processing unit, are distributed along a communication link by way of which the transfer of information from one processor module to another processor module is effected, characterized in that each of said processor modules includes a communications interface unit coupled to said communication link and the data processing unit of that module and which carries out the transmission and reception of messages assigned a predetermined priority level between the data processor of that processor module and another processor module, and wherein each of said interface units include;

• means for repetitively generating in the same time-frame a plurality of time-slots preassigned to and defining the address of each of said data processor modules,
• means for recognizing the repetitive occurrence of the time slot preassigned to that processor module;
• means for enabling each communication interface unit, in response to a transmission control signal from its associated data processing unit to transmit a message including a priority code component defining the priority level of the message over said communication link during the occurrence of its preassigned time-slot;
• means responsive to the generation of the transmission control signal for causing that interface unit of the data processor module to which said message is addressed to receive and store said message in the addressed data processor module;
• and means responsive to receiving said priority code component for changing the priority level of the messages to be stored in the data processor module.