Multilayered glass-ceramic substrate for mounting of semiconductor device
AssigneeInternational Business Machines Corporation
InventorsBernt Narken, Rao R. Tummala
Life of this patent
Estimating the term…
Abstract
A method for fabricating an interconnection package for a plurality of semiconductor chips which include the fabrication of a multi-layered glass-ceramic superstructure with a multi-layered distribution of conductors on a preformed multi-layered glass-ceramic base, by the repeatable steps of depositing a conductor pattern on the base and forming thereon a crystallizable glass dielectric layer which is then crystallized to a glass-ceramic prior to further additions of conductor patterns and crystallizable glass layers to form a monolithic compatible substrate all through. Semiconductor chips can be electrically connected to expose conductor patterns at the top surface of the resultant glass-ceramic package.
Claims13
A method for fabricating a solid thermally compatible and integral glass-ceramic/metal electrical interconnection package adapted for bonding to semiconductor integrated circuit chips, comprising the steps of:
- (a) providing a glass-ceramic substrate having a plurality of metallized conductive planes interconnected together in a predetermined pattern,
- (b) forming a coating of a first metallized conductive pattern on the upper surface of said substrate in a predetermined pattern of interconnection to said planes,
- (c) forming a plurality of vertical conductive studs on said surface and coating in a predetermined pattern of interconnection to said conductive planes and coating,
- (d) forming a crystallizable glass layer on said surface having a temperature of crystallization below the melting point of said conductive coating and studs, wherein said substrate and said layer are selected from a glass-ceramic having either .beta.-spodumene or cordierite as the principle crystalline phase,
- (e) heating said glass layer to the crystallization temperature thereof for sufficient time to crystallize said glass into a bubble-free glass-ceramic layer, said crystallization being effected without reflow of any underlying glass-ceramic layers or disruption of any lower levels of metallization and
- (f) conditioning said glass-ceramic layer to expose at the top surface thereof said vertical conductive studs.
A method for fabricating a solid all glass-ceramic/metal electrical interconnection package adapted for electrical connection to semiconductor integrated circuit chips, comprising the steps of:
- (a) providing a glass-ceramic substrate having a plurality of metallized planes interconnected together in a predetermined pattern,
- (b) forming a coating of a first metallized pattern on the upper surface of said substrate in a predetermined pattern of interconnection to said conductive planes,
- (c) forming a plurality of conductive studs on said surface and coating in a predetermined pattern of interconnection to said conductive planes and coating,
- (d) forming over said surface a crystallizable glass layer having a temperature of crystallization below the melting point of said conductive coating and studs, wherein said substrate and said layer are selected from glass-ceramics having either .beta.-spodumene or cordierite as the principle crystalline phase,
- (e) heating said glass layer to the crystallization temperature thereof for sufficient time to crystallize said glass layer into a bubble-free glass-ceramic layer, said crystallization being effected without reflow of any underlying glass-ceramic layers or disruption of any lower levels of metallization,
- (f) conditioning said glass-ceramic layer to expose at the top surface thereof said studs,
- (g) forming on the exposed surface of the glass-ceramic layer an additional coating of a metallized pattern in a predetermined pattern of interconnection to underlying conductive planes, patterns and studs,
- (h) forming a plurality of additional conductive studs on the said exposed glass-ceramic surface in a predetermined pattern of interconnection to underlying conductive planes, pattern and studs,
- (i) forming over the underlying glass-ceramic layer an additional layer of said crystallizable glass having a temperature of crystallization below the melting point of the underlying conductive coatings and studs,
- (j) heating said additional layer of glass to the crystallization temperature thereof for sufficient time to crystallize the glass layer into an additional bubble-free glass-ceramic layer, said crystallization being effected without reflow of any underlying glass-ceramic layers or disruption of any lower levels of metallization, and
- (k) conditioning said additional glass-ceramic layer to expose at the top surface thereof the immediate underlying studs.
Dependencies are inferred from the claim text.