Self-correcting solid-state mass memory organized by words for a stored-program control system

A self-correcting, solid-state mass memory, organized in words for a stored-program control system wherein a processor is interfaced towards the mass memory through a controller, said mass memory including at least one memory module, a control module and a bidirectional internal bus connecting the control module to each memory module, said memory module comprising:

• at least one row of integrated memory circuits realized by charge-coupled technology and consisting of blocks of shift registers organized in serial-parallel-serial configuration, each block being able to be addressed randomly and at the same time as the blocks of equal position in all the circuits of the row and containing a plurality of cells that can be sequentially addressed, each circuit storing a bit out of a plurality of words consisting of information and redundancy bits, each row comprising as many circuits as there are bits in said words;
• and
• first input/output means able to connect said circuits to said internal bus;
• the control module comprising:
• a microprogrammed time base designed to generate the timing and enabling signals necessary to the operation of the memory unit, such signals having variable shape and period depending on the type of operation;
• an addressing control circuit that, on the basis of the information received from the controller and from the time base, generates the addresses for reading and writing in the memory module and memory circuits;
• second input/output means designed to connect said control module to the internal bus and distribute the data towards the memory module or towards the controller;
• and
• a self-correcting logic able to generate the redundancy bits on the basis of the information bits and to control, by using said redundancy bits, the good operation of the memory module and to correct possible memory errors.