Integrated digital multiplier circuit using current mode logic
AssigneeTRW Inc.
InventorJohn J. Muramatsu
Life of this patent
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Abstract
A parallel digital multiplier circuit fabricated in accordance with an advanced triple diffusion process providing feature geometry down to a minimum of two microns and junction depths of less than two microns, wherein a high packing density provided by the fabrication process is utilized to full advantage by the use of current mode logic, which requires relatively few and relatively small resistors, uses only inherently faster NPN transistors, employs a relatively small voltage swing between logic levels, has unlimited cascading capability, and provides a superior speed-power product.
Claims8
For use in a monolithic integrated multiplier circuit, the combination of:
- a plurality of NPN transistors and resistors fabricated in accordance with a high-density triple diffusion process allowing for use of a two-micron minimum geometry, and correspondingly small junction depths, to provide a very high packing density and a corresponding low defect rate and low production cost;
- and
- circuit means for connecting said transistors and resistors to operate in current mode logic, to provide a circuit with fewer and smaller resistors, and a desirably low speed-power product.
A monolithic integrated multiplier circuit comprising:
- a plurality of NPN transistor devices;
- and
- a plurality of resistance devices;
- said transistor devices and resistance devices being interconnected in current mode logic to form a multiplier circuit having a low speed-power product and being capable of performing parallel multiplication of two multi-digit numerical input quantities, to produce a multi-digit numerical output quantity, and said transistor and resistance devices being formed on a single substrate by a triple diffusion process providing for as low as two-micron feature widths and spacings, for high packing density and a corresponding low defect rate and low production cost, and wherein said resistance devices are formed as unpinched n-type diffusion regions in said substrate, to maintain the high density, low defect rate and low production cost.
Dependencies are inferred from the claim text.