US 4,215,399 AGranted

Special function control system for a dual microprocessor programmable process control system

AssigneeTexas Instruments Incorporated

InventorsMark J. Pavicic, Jack L. Mahaffey, II

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Abstract

An intelligent programmable process control system including a first microprocessor which scans and executes a sequence of boolean logic functions and a second microprocessor which performs complex operations including arithmetic computations beyond the capabilities of the first microprocessor. The first microprocessor transmits interrupt requests to the second microprocessor when a scanned sequence instruction requires complex operations to be performed. First flag bit register indicates to the first microprocessor that a requested operation has been queued-up. Second flag bit register indicates to the first microprocessor that the requested operation has been completed. When the first microprocessor requires complex operations, it checks the state of a respective first flag bit register to determine whether the complex operation has already been queued-up and if so, checks the state of a respective second flag bit register to determine whether the queued-up function has been completed by the second microprocessor. If the complex operation has been queued-up and the second flag bit indicates that the operation has not been completed, the first microprocessor continues scanning and executing its sequence of functions asynchronously with respect to the second microprocessor. If the first flag bit indicates that the operation has not been queued-up, then the first microprocessor transmits an interrupt request to the second microprocessor.

Claims26

Dependent claims

An intelligent programmable process control system responsive to the states of sensors located along a process for controlling the states of controllable devices located along said process, said system comprising:

(a) first microprocessor means for scanning and executing a sequence of boolean logic functions;
(b) second microprocessor means for performing relatively complex operations including arithmetic computations beyond the capabilities of said first microprocessor means, said first microprocessor means being coupled to an interrupt request input means of said second microprocessor means for transmitting interrupt requests to said second microprocessor means for execution of selection of said complex operations;
(c) addressable memory means, said first and second microprocessor means being coupled to said addressable memory means to communicate with each other via selectively addressed memory locations of said memory means;
(d) flag bit register means settable by said second microprocessor means and detectable by said first microprocessor means for indicating to said first microprocessor means that a requested complex operation has been queued-up in the task queue of said second microprocessor means;
wherein
(e) said first microprocessor means includes means responsive to the encountering of a complex operation in said sequence of boolean logic functions for:
(i) checking said flag bit register means to determine whether such complex operation has been queued-up in the task queue of said second microprocessor means;
and
(ii) transmitting an interrupt request to said second microprocessor means only if such complex operation is not in the task queue of said second microprocessor means as determined by the state of said first flag bit register means;
(iii) checking said second flag bit register means to determine whether a queued-up complex operation has been completed by said second microprocessor means, said first microprocessor means continuing to scan and execute its sequence of boolean logic functions asynchronously with respect to the operation of said second microprocessor means until said second flag bit register means indicates that execution of a requested complex operation has been completed by said second microprocessor means.

7 more elements

(a) first microprocessor means for scanning and executing a sequence of boolean logic functions;
(b) second microprocessor means for performing relatively complex operations including arithmetic computations beyond the capabilities of said first microprocessor means, said first microprocessor means being coupled to an interrupt request input means of said second microprocessor means for transmitting interrupt requests to said second microprocessor means for execution of selection of said complex operations;
(c) addressable memory means, said first and second microprocessor means being coupled to said addressable memory means to communicate with each other via selectively addressed memory locations of said memory means;
and
(d) flag bit register means settable by said second microprocessor means and detectable by said first microprocessor means for indicating to said first microprocessor means that a requested complex operation has been completed by said second microprocessor means, wherein;
(e) said first microprocessor means includes means responsive to the encountering of a complex operation in said sequence of boolean logic functions for checking said flag bit register means to determine whether a queued-up complex operation has been completed by said second microprocessor means, said first microprocessor means continuing to scan and execute its sequence of boolean logic functions asynchronously with respect to the operation of said second microprocessor means until said flag bit register means indicates that execution of a requested complex operation has been completed by said second microprocessor means.

3 more elements

(a) first microprocessor means for scanning and executing a sequence of boolean logic functions;
(b) second microprocessor means for performing relatively complex operations including arithmetic computations beyond the capabilities of said first microprocessor means, said first microprocessor means being coupled to an interrupt request input means of said second microprocessor means for transmitting interrupt requests to said second microprocessor means for execution of selection of said complex operations;
(c) addressable memory means, said first and second microprocessor means being coupled to said addressable memory means to communicate with each other via selectively addressed memory locations of said memory means;
(d) first flag bit register means settable by said second microprocessor means and detectable by said first microprocessor means for indicating to said first microprocessor means that a requested complex operation has been queued-up in the task queue of said second microprocessor means;
and
(e) second flag bit register means settable by said second microprocessor means and detectable by said first microprocessor means for indicating to said first microprocessor means that a requested complex operation has been completed by said second microprocessor means;
wherein
(f) said first microprocessor means includes means responsive to the encountering of a complex operation in said sequence of boolean logic functions for:
(i) checking said first flag bit register means to determine whether such complex operation has been queued-up in the task queue of said second microprocessor means;
(ii) transmitting an interrupt request to said second microprocessor means only if such complex operation is not in the task queue of said second microprocessor means as determined by the state of said first flag bit register means;
(iii) checking said second flag bit register means to determine whether a queued-up complex operation has been completed by said second microprocessor means, said first microprocessor means continuing to scan and execute its sequence of boolean logic functions asynchronously with respect to the operation of said second microprocessor means until said second flag bit register means indicates that execution of a requested complex operation has been completed by said second microprocessor means.

8 more elements

Dependencies are inferred from the claim text.