Lattice filter for waveform or speech synthesis circuits using digital logic

A method of generating human-like sounds from a digital excitation signal, a digital amplitude signal and N digital filter coefficients in an electronic filter, said method comprising the steps of:

• (a) repetitively initiating 2N multiply operations with an multiplier using all but one of the digital filter coefficients as one operator twice during the 2N operations, using said one of the digital filter coefficients once as one operator during the 2N operations and using said digital amplitude signal once as one operator during the 2N operations;
• (b) repetitively initiating an arithmetic operation in an arithmetic circuit using the results of the multiply operation as an operator in the arithmetic operation;
• (c) temporarily storing selected data outputted from the arithmetic circuit;
• (d) repetitively using temporarily stored data outputted from the arithmetic circuit as another operator in said multiplier during N of said 2N operations;
• (e) repetitively using data outputted from the arithmetic circuit as another operator in said multiplier during N-1 of said 2N operations;
• (f) repetitively using the digital excitation signal as another operator in said multiplier once during each 2N operations, said digital excitation signal being multiplied with said digital amplitude signal;
• and
• (g) converting selected ones of the results of the arithmetic operations performed by said arithmetic circuit to sound.

A digital filter responsive to a digital excitation signal and to a plurality of digital values representing filter coefficients, said filter comprising;

• (a) a first memory for storing said plurality of digital values;
• (b) a multiplier circuit;
• (c) first circuit means for coupling said first memory and said multiplier circuit;
• (d) an arithmetic circuit having an input coupled to said multiplier circuit;
• (e) a digital storage means for storing data outputted from said arithmetic circuit;
• and
• (f) second circuit means for selectively coupling the outputs of said digital storage means and said arithmetic circuit to an input of said multiplier circuit.

A digital filter for implementing a lattice filter responsive to a digital excitation signal, an amplification factor and to a plurality of digital values representing filter coefficients, said filter comprising:

• (a) a first memory for storing said plurality of digital values and said amplification factor;
• (b) a multiplier circuit;
• (c) a first circuit means for coupling said first memory and said multiplier circuit;
• (d) an arithmetic circuit having an input coupled to said multiplier circuit;
• (e) a digital storage means for storing data outputted from said arithmetic circuit;
• and
• (f) second circuit means for selectively coupling the output of said digital storage means, the output of said arithmetic circuit and said excitation signal to an input of said multiplier circuit.

A digital filter for implementing a lattice filter responsive to a digital excitation signal and to a plurality of digital values representing filter coefficients, said filter comprising:

• (a) a first memory for storing said plurality of digital values;
• (b) a multiplier circuit;
• (c) first circuit means for coupling said first memory and said multiplier circuit;
• (d) an arithmetic circuit having an input coupled to said multiplier circuit;
• (e) a digital storage means for storing data outputted from said arithmetic circuit;
• (f) second circuit means for selectively coupling the outputs of said digital storage means and said arithmetic circuit to an input of said multiplier circuit;
• and
• (g) third circuit means for selectively coupling the outputs of said digital storage means, the output of said arithmetic circuit and said excitation signal to another input of said arithmetic circuit.

A digital filter responsive to a digital excitation signal and to a plurality of digital values representing filter coefficients, said filter comprising:

• (a) a multiplier circuit;
• (b) an adder/subtractor circuit coupled at a first input thereof to the output of said multiplier circuit;
• (c) first delay circuit means coupled to the output of said adder/subtractor circuit;
• (d) second delay circuit means coupled to receive data outputted from said adder/subtractor circuit, the delay associated with said second delay circuit means being longer than the delay associated with said first delay circuit means;
• (e) latch storage means for temporarily storing data outputted from said second delay circuit means;
• (f) first switching means for selectively coupling the output of said latch storage means, the output of said first delay circuit means and the output of said adder/subtractor circuit to a first input of said multiplier circuit;
• (g) second switching means for selectively coupling the output of said latch storage means, the output of said adder/subtractor circuit and said second delay circuit means to a second input of said adder/subtractor circuit;
• and
• (h) a memory means coupled to a second input of said multiplier circuit, for storing said digital values representing the filter coefficients.

A digital filter for a speech synthesis circuit, said filter being responsive to a digital excitation signal and to a plurality of digital values representing filter coefficients, said filter comprising:

• (a) a multiplier circuit;
• (b) an adder/subtractor circuit coupled at a first input thereof to the output of said multiplier circuit;
• (c) delay circuit means coupled to the output of said adder/subtractor circuit;
• (d) latch storage means for temporarily storing data outputted from said delay circuit means;
• (e) first switching means for selectively coupling the output of said latch storage means, the output of said first delay circuit means and the output of said adder/subtractor circuit to a first input of said multiplier circuit;
• (f) second switching means for selectively coupling the output of said latch storage means, the output of said adder/subtractor circuit and said delay circuit means to a second input of said adder/subtractor circuit;
• (g) a memory means coupled to a second input of said multiplier circuit, for storing said digital values representing the filter coefficients;
• and
• (h) digital to analog converter means coupled to the output of said latch storage means.

A digital filter responsive to time period timing signals and to a plurality of digital values representing filter coefficients, said filter being equivalent to an N stage lattice filter and comprising:

• (a) an array multiplier having M stages;
• (b) an adder/subtractor circuit coupled at a first input thereof to the output of said multiplier;
• (c) first delay circuit means having a delay of N-M-2 time periods and coupled to the output of said adder/subtractor circuit;
• (d) second delay circuit means coupled to the output of said first delay circuit means;
• (e) third delay circuit means coupled to the output of said second delay circuit means, the delay associated with said third delay circuit means being equal to N+M-1 time periods;
• (f) latch storage means for temporarily storing selected data outputted from said adder/subtractor circuit;
• (g) first switching means for selectively coupling the output of said latch storage means, the output of said second delay circuit means and the output of said first delay circuit means to a first input of said multiplier circuit;
• (h) second switching means for selectively coupling the output of said latch storage means, the output of said adder/subtractor circuit and the output of said third delay circuit means to a second input of said adder/subtractor circuit;
• and
• (i) means coupled to a second input of said multiplier circuit for applying said digital values representing filter coefficients thereto.

A digital filter responsive to a digital excitation signal and to a plurality of digital values representing filter coefficients, said filter comprising:

• (a) a digital array multiplier;
• (b) coupling means for coupling said filter coefficients to one input of said multiplier;
• (c) arithmetic means for performing arithmetic operations on data outputted from said multiplier;
• (d) first delay circuit means for temporarily storing at least a portion of the results of the arithmetic operations performed by said arithmetic means;
• (e) first switching means for selectively coupling the output of said first delay circuit means to another input of said multiplier;
• (f) second delay circuit means for temporarily storing at least a portion of the results of the arithmetic operations performed by said arithmetic means, said second delay circuit means storage said results for a longer period of time than said first delay circuit means;
• (g) second switching means for selectively coupling the output of said second delay circuit means to an input of said arithmetic means;
• and
• (h) filter output means for outputting a selected portion of said results of the arithmetic operations performed by said arithmetic means.

A digital filter for implementing an N stage lattice filter comprising:

• (a) a multiplier circuit;
• (b) a memory means for storing filter coefficients;
• (c) means coupling said memory means to an input of said multiplier circuit;
• (d) arithmetic means for performing arithmetic operations on data outputted from said multiplier circuit;
• (e) first delay circuit means for temporarily storing at least a portion of the results of the arithmetic operations performed by said arithmetic means;
• (f) first switching means for selectively coupling the output of said first delay circuit means to another input of said multiplier circuit;
• (g) second delay circuit means for temporarily storing at least a portion of the results of the arithmetic means, said second delay circuit means storing said results for a longer period of time than said first delay circuit means;
• and
• (h) second switching means for selectively coupling the output of said second delay circuit means to an input of said arithmetic means;
• and
• (i) filter output means for outputting a preselected portion of said results of the arithmetic operations performed by said arithmetic means.