Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching

A method for forming double diffused field effect transistor integrated circuit structure comprising:

• providing a silicon body having a pattern of monocrystalline silicon regions isolated from one another by dielectric isolation;
• forming on said body a first insulator layer;
• forming openings in said insulator layer in areas where source and drain for said field effect transistor are to be formed and which result in first insulator regions having substantially horizontal surfaces and substantially vertical surfaces;
• diffusing a P type impurity through said openings to form P regions in said silicon body;
• forming a second insulator layer composed of a material different from said first insulator on both said substantially horizontal surfaces and said substantially vertical surfaces;
• reactive ion etching said second layer to substantially remove said horizontal layer and to provide a narrow dimensioned second insulator region on said silicon body;
• diffusing an N type impurity through the said openings which have been reduced in size by said narrow dimensioned second insulator region on said silicon body to form N type regions in said silicon body which are deeper and narrower than said P type regions;
• and
• forming contacts to said sources and drains and making a gate electrode on the first insulator between each of the sources and drains.

A method for forming double diffused field effect transistor integrated circuit structure comprising:

• providing a silicon body having a pattern of monocrystalline silicon regions isolated from one another by dielectric isolation;
• forming on said body a first insulator layer;
• forming openings in said insulator layer in areas where source and drain for said field effect transistor are to be formed and which result in first insulator regions having substantially horizontal surfaces and substantially vertical surfaces;
• diffusing a N type impurity through said openings to form N regions in said silicon body;
• forming a second insulator layer composed of a material different from said first insulator on both said substantially horizontal surfaces and said substantially vertical surfaces;
• reactive ion etching said second layer to substantially remove said horizontal layer and to provide a narrow dimensioned second insulator region on said silicon body;
• diffusing a P type impurity through the said openings which have been reduced in size by said narrow dimensioned second insulator region on said silicon body to form P type regions in said silicon body which are deeper and narrower than said N type regions;
• and
• forming contacts to said sources and drains and making a gate electrode on the first insulator between each of the sources and drains.

A method for forming a bipolar integrated circuit structure having submicrometer emitters comprising:

• providing a silicon body having a pattern of monocrystalline silicon regions isolated from one another by dielectric isolation;
• providing a base region within certain of said monocrystalline regions separated from a collector reach-through region by dielectric isolation;
• forming on said body first layer having substantially horizontal surfaces and substantially vertical surfaces;
• forming a second layer composed of an insulator material and of a material different from said first layer on both said substantially horizontal surfaces and said substantially vertical surfaces;
• reactive ion etching said second layer to substantially remove said horizontal layer and to provide narrow dimensioned second insulator regions on said silicon body in the areas designated to be said emitters;
• thermally oxidizing the exposed surfaces of said silicon body;
• removing said narrow dimensioned second regions to form said narrow dimensioned mask openings;
• and
• forming said emitters through said mask openings.