Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system

In a system comprising at least a first and second CPU;

• shared input/output devices;
• at least a first and second set of fan-out paths (channels), each path set coupling a corresponding CPU as a source node;
• and at least a first and second control node, each control node including means for accessing the devices and for selectively intercepting predetermined paths from either set for completing a signal path connection to a single destination device;
• each CPU, path, control node and device having at least one interface operable as a boundary sharable with a connecting system element for the transfer of information;
• characterized in that
• each control node includes:
• memory means for storing a map of the CPU, node, and path connections;
• means for modifying the map responsive to allegiance information from at least one CPU (SHID, SNID) communicated to the control node over an intercepted path and for generating and maintaining CPU and device identity and priority of connection information;
• and
• means for completing the signal path connection for any given reservation or reconnection indication respectively from an originating CPU or available device by accessing the map for ascertaining whether the CPU is a member of a set of interfaces to which the device is reserved and then selecting a path, if available.

A method for path independent reservation and reconnection of input/output devices by CPU's operating in a multi-CPU and shared device access system, the system including multiple control units, each control unit further including multiple channel/control unit interfaces and control unit/device interfaces, each channel/control unit interface communicating with one CPU while each control unit/device interface communicates with a selected one of the devices, the operating system of each CPU being capable of initiating communications with a device by a START I/O instruction, the execution of this instruction thereby causing control to be relinquished to a series of channel command words (CCW's), said series of channel command words, in turn, being sent to the control unit over the channel/control unit interface for selecting and accessing the device, said multi-CPU's, channels, control units, and devices forming a control and data pathing network, a CPU reserving a device or a device indicating availability for reconnection by respectively communicating a signal over the appropriate interfaces to the intercepting control unit;

• characterized in that
• the method comprises the steps of:
• forming a map of network topology (FIG. 3) and storing said map at a control unit (FIG. 2, Element 25') in the network common to at least a pair of CPU's connectable over requisite channel/control unit interfaces;
• generating and maintaining CPU and device identity and priority of connection information (FIGS. 4 and 5);
• managing the connection of CPU's to devices such that for any given reservation or reconnection indication, the map is accessed by at least one control unit for ascertaining the path set to which connection or reconnection is possible;
• and
• selecting an available path if the CPU is a member of the set of interfaces to which the device is reserved.

A method of path independent reservation and reconnection of shared access devices by CPU's for use in a system of the type comprising at least a first and second CPU;

• a first and second plurality of channels, each plurality of channels coupling a corresponding CPU;
• a plurality of input/output devices;
• and first and second control units terminating at least one channel, each CPU channel, device, and control unit having at least one interface operable as a boundary sharable with a connecting system element for the transfer of information;
• said control unit including means for accessing the devices and for switchably interconnecting channel and device interfaces;
• said method comprising the steps of:
• forming a map of CPU, control unit, and device connectability, and storing said map at a control unit common to at least a pair of CPU's and connectable over requisite channels;
• selecting a device by an initiating CPU in which the control unit completes a signal path connection to the destination device by switchably interconnecting channel and device interfaces;
• disconnecting the channel from the control unit responsive to device access requests from the CPU and recording the device address and CPU allegiance of the accessed device by the control unit, allegiance constituting an a priori association among a given CPU and at least one device to process reservations and accesses to the exclusion of all other CPU's;
• causing the destination device to access information as requested by the initiating CPU in a disconnected mode from the control unit and the posting of a completion signal upon satisfaction of the access request;
• polling of device status by either one or both of the control units;
• and
• raising a reconnection request on those channels terminating in the respective control units which are associated with the device as determined from the previously recorded device address and CPU allegiance.

In a system comprising at least one CPU partitionable into two logical processors;

• a first and second channel coupling the CPU;
• a plurality of input/output devices;
• a first and second control unit terminating the channels, each control unit including means for accessing the devices and for switchably interconnecting device and channel interfaces, each CPU, channel, device, and control unit having at least one interface operable as a boundary sharable with a connecting system element for the transfer of information, wherein the method for path independent reservation and reconnection of shared access devices by the logical processors comprises the steps of:
• forming a map of logical processor, control unit, and device connectability and storing said map for access by each control unit;
• selecting a device by an initiating logical processor in which an available control unit completes a signal path connection to the destination device by switchably interconnecting channel and device interfaces;
• disconnecting the channel from the control unit responsive to device access requests from the logical processor and recording the device identity and logical processor allegiance of the accessed device by the control unit, said allegiance constituting an a priori association among a given CPU and at least one device for processing reservations and accesses to the exclusion of all other CPU's;
• causing the destination device to access information as requested by the initiating logical processor in a disconnected mode from the control unit and the posting of a completion signal upon satisfaction of the access request;
• polling of device status by either one or both of the control units;
• and
• raising a reconnection request on those channels terminating the respective control units which are associated with the device as determined from the previously recorded device identity and logical processor allegiance.