US 4,207,556 AGranted

Programmable logic array arrangement

AssigneeNippon Telegraph & Telephone Public Corporation

InventorsYoshi Sugiyama, Keisuke Kataoka

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Abstract

The programmable logic array arrangement comprises a plurality of cell units formed on a semiconductor substrate and wiring means for interconnecting the cell units. Each cell unit comprises a plurality of electronic elements such as resistors, transistors and diodes which are necessary to form logic circuits, and the wiring means comprises a plurality of bit lines and product term lines which are arranged in the form of a matrix, conductive layers for determining the type and input/output conditions of the logic circuit to be formed. The array arrangement further comprises a group of switching elements connected between the electronic element, bit lines, product term lines, and conductive layers for interconnecting or disconnecting these elements thereby forming desired logic circuits.

Claims14

Dependent claims

A programmable logic array arrangement, comprising:

a wiring matrix including a plurality of row lines and a plurality of column lines, the row and column lines being arranged in a matrix and including at least two conductive layers;
and
a plurality of cell units, each cell unit including;
a function unit including;
a first plurality of electronic elements;
and
a first plurality of switching elements for selectively connecting each of the first plurality of electronic elements to said row and column lines;
said electronic elements and switching elements being arranged with respect to the wiring matrix so that both OR functions and AND functions may be implemented by each function unit by activating appropriate switching elements;
and
an array unit including:
a second plurality of electronic elements;
and
a second plurality of switching elements for selectively connecting said second plurality of electronic elements to said row and column lines;
said second plurality of electronic elements and said second plurality of switching elements being arranged so that a plurality of different logic functions can be implemented in an array unit by activating the appropriate ones of said second plurality of switching elements.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 05/857,306Filed 5 Dec 1977
Priority: JP 51-14944114 Dec 1976
Granted: 10 Jun 1980
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 84/901
Masterslice integrated circuits: comprising bipolar technology
H03K 19/17708
The logic functions being realised by the interconnection of rows and columns: using an AND matrix followed by an OR matrix, i.e. programmable…
H10W 20/49
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes: adaptable…
H10W 20/493
Adaptable interconnections, e.g. fuses or antifuses: fuses, i.e. interconnections changeable from conductive to non-conductive