Circuit for limiting voltage differential in differential amplifiers

The combination comprising:

• first and second power terminals for the application therebetween of an operating potential;
• first and second input terminals for the application of differential signals therebetween;
• first, second, third, and fourth transistors each transistor having first and second electrodes defining the ends of a conduction channel overlying a substrate region and having a control electrode isolated from and overlying said conduction channel;
• means connecting said first and second transistors in a differential amplifier configuration including means connecting the first electrodes of said first and second transistors to a common point and means connected between said common point and said first power terminal for passing a current between said common point and said first power terminal;
• means connecting one of the first and second electrodes of said third transistor to the control electrode of said first transistor and the other of said first and second electrodes of said third transistor to said first input terminal;
• means connecting one of the first and second electrodes of said fourth transistor to the control electrode of said first transistor and the other of said first and second electrodes of said third transistor to said common point;
• means connecting the control electrode of said third transistor to said common point;
• means connecting the control electrode of said fourth transistor to said first input terminal;
• and
• means connecting the control electrode of said second transistor to said second input terminal.

In combination with two insulated-gate field-effect transistors (IGFETs) interconnected to form a differential amplifier, the source electrodes of the two IGFETs being connected to a common point which is returned via a conduction path to a point of reference potential, an improved circuit for limiting the maximum potential difference that an input signal can generate between the gate electrodes of the two IGFETs comprising:

• first and second input terminals between which said input signal may be applied;
• means connected between the gate electrode of one of the two IGFETs and said first input terminal for decoupling the input signal from the gate electrode when the input signal is of a given magnitude and of a polarity to turn-off said one IGFET;
• means connected between the gate electrode of said one IGFET and said common point for clamping the gate electrode of said one IGFET to said common point when the input signal increases above said given magnitude and is of a polarity to further turn-off said one IGFET;
• and means coupling the gate electrode of the other IGFET to said second input terminal.