Multi-instruction stream branch processing mechanism

In a computer system having storage, instruction processor, and execution unit, said instruction processor including a plurality of instruction buffers with buffer selection and instruction fetching means, each instruction buffer being responsive to said buffer selection means to receive and store, concurrently, at least one instruction from an independent sequence of instructions from said storage, an instruction decoder, instruction gate means interconnecting said instruction decoder and a selected one of said instruction buffers, and an instruction queue comprised of a plurality of queue registers, each said queue register storing execution control information received from said instruction decoder for each instruction decoded, said execution unit including control means, responsive to said execution control information received from each said queue register, for performing the function called for by each said instruction, and providing to said instruction processor, result signals for certain of said instructions, instruction sequencing logic comprising:

• branch signalling means, responsive to a branch instruction in said instruction decoder received from a first one of said instruction buffers, for controlling said buffer selection and instruction fetching means to transfer a target instruction from said storage to another of said instruction buffers;
• instruction gate control means connected to said instruction gate means, for transferring a next instruction to said instruction decoder after transfer of said execution control information of said branch instruction to said instruction queue;
• target buffer indicating means responsive to said branch signalling means, associated with each of said queue registers when storing execution control information of a branch instruction, for indicating said another of said instruction buffer means;
• and
• instruction selection means, responsive to said result signals from said execution unit in response to said branch instruction and said associated target buffer indicating means, for selecting the next sequential execution control information to be transferred to said execution unit.