Digital signal detector

A detector for a digital signal transmitted in a serial bit stream at a predetermined bit frequency by a clock signal, comprising:

• first counting means responsive to the clock signal for providing a reset pulse signal at the end of each N bit interval, where N is an integer;
• transition detection means responsive to the digital signal and the clock signal for providing a transition pulse signal for each change in logical state between successive bits of the digital signal;
• window generating means responsive to the clock signal for repetitively generating during each bit interval at least first, second and third non-overlapping window signals, the first window signal substantially centered about the transition of the clock signal that is in synchronism with the bit transitions of the digital signal, the second window signal substantially centered about the transition of the clock signal that is in quadrature with the bit transitions of the digital signal, the third window signal disposed between the first and second window signals, the intervals of the first and second window signals being substantially identical, and the interval of the third window signal being smaller than the intervals of the first and second window signals, the first window signal having a corresponding value of +1, the second window having a corresponding value of -1 and the third window signal having a corresponding value of zero;
• second counting means responsive to the reset pulse signals and transition pulse signals for providing for each N bit interval, a totallized count formed by totallizing for each transition pulse signal, the value corresponding to the window signals during which the respective transition pulse signal occurs;
• and
• means for comparing each totallized count from the second counting means to a first threshold count and providing an indication signal indicating that the digital signal is present when the respective totallized count is greater than the first threshold count.