Device for discrete control of thyristor-pulse converters

A device for discrete control of thyristor-pulse converters, each converter comprising power thyristors, comprising:

• a master pulse generator having an output;
• a control unit having an add output and a subtract output;
• a clock pulse counter having a complementing input, a control output and a plurality of logic outputs whose number is equal to twice the number of digits, the complementing input of said clock pulse counter being connected to the output of said master generator, and the control input being connected to the power thyristor of one of said thyristor-pulse converters;
• a bidirectional pulse counter having an add input, a subtract input, a reset input receiving a signal resetting the bidirectional pulse counter, a setting input receiving a signal setting the bidirectional pulse counter to its final state, a first output producing a signal at the first control phase, a second output producing a control start signal, a third output producing a signal indicative of the maximum pulse duration being attained, a fourth output producing a signal indicative of the state of the bidirectional pulse counter, corresponding to the maximum pulse duration of the output parameter of one of said thyristor-pulse converters, and a plurality of logic outputs whose number is equal to the number of logic outputs of said clock pulse counter and is equal to twice the number of digits, said bidirectional pulse counter being connected through said add input and said subtract input to the add output and the subtract output of said control unit, respectively;
• a decoder matching the operation of said clock pulse counter and said bidirectional pulse counter, and having a plurality of inputs, a first output bus producing a signal determining the initial pulse duration, a second output bus producing a signal determining the penultimate value of the pulse duration, and a third output bus producing a signal determining the maximum pulse duration, said decoder being connected through said inputs to the logic outputs of said clock pulse counter and to the logic outputs of said bidirectional pulse counter;
• a first individual AND gate having a first input, a second input and an output, and being connected through its first input to the control output of said clock pulse counter and connected through its output to said power thyristor of a second thyristor-pulse converter;
• first and second groups of AND gates, the number of AND gates in each group being determined by the number of digits of said clock pulse counter and said bidirectional pulse counter and by the reuired control range of the output parameter of said thyristor-pulse converters, each AND gate of said groups having a first input, a second input and an output, said first input being connected to said first output bus of said decoder;
• a NOT gate having an input and an output, said input being connected to the third output bus of said decoder;
• a sign flip-flop having a first input, a second input, a first output and a second output, the first output of said sign flip-flop being connected to the second inputs of said AND gates of the first group, the second output being connected to the second input of said first individual AND gate, to the second inputs of said AND gates of the second group, and to the reset input of said bidirectional pulse count;
• a second individual AND gate having a first input, a second input and an output, the first input being connected to the output of said NOT gate, the second input being connected to the second output of said bidirectional pulse counter, and the output being connected to the first input of said sign flip-flop;
• a third individual AND gate having a first input, a second input and an output, the first input being connected to the add output of said control unit, the second input being connected to the third output of said bidirectional pulse counter, and the output of said third AND gate being connected to the second input of said sign flip-flop;
• a fourth individual AND gate having a first input, a second input, a third input, and an output, the first input of said fourth AND gate being connected to the subtract output of said control unit, the second input being connected to the first output of said bidirectional pulse counter, the third input being connected to said fourth output of said bidirectional pulse counter, and the output being connected to the first input of said sign flip-flop and to the setting input of said bidirectional pulse counter;
• and
• a circuit for passing the time-shifted trains of control pulses fed from the output buses of said decoder to the power thyristors of said thyristor-pulse converters, said circuit including at lease one OR gate, each OR gate of said circuit having inputs, the number of inputs being equal to the number of AND gates in said groups, each said OR gate of said circuit being connected through said inputs to the outputs of said AND gates of one of said groups and being connected through an output to said power thyristor of one of said thyristor-pulse converters.