US 4,194,113 A · Method and apparatus for isolating faults in a logic circuit

Abstract

A portable processor-oriented digital tester and method for isolating faults in digital printed circuit boards under test. The digital tester includes a processor, a main memory and a plurality of driver/sensor circuits. The main memory stores a signature file containing known correct signatures for the nodes of a board under test and also stores an image file which contains information defining the topology of the board under test. The driver/sensor circuits are programmable to receive test information generated by a test program stored in the main memory, transmit such information to inputs of a board under test, and receive information produced by the board under test in response to the input test information. The response received from outputs of the board under test is compared to a corresponding known-correct response to identify a faulty output of the board under test. The processor refers to the image file to identify a logic element driving the faulty output and to identify the nodes which are inputs to the logic element. The processor causes instructions to be displayed to the operator of the portable digital tester to instruct the operator to probe the input nodes of the logic element. A signature is generated for each node and compared to a corresponding known correct signature for that node as it is probed by the operator to identify a faulty input node. For each faulty node found, the measured signature, the initial state, and a number equal to the smaller of an input test number of the known correct initial transition of the faulty node and an input test number of the first incorrect transition of the faulty node is stored in a history file having pointers to the image file for each node. If a component is found having a faulty output and all good inputs, that component is identified as defective. If a loop is identified by the main processor, the operator is instructed to test all external inputs to the loop; if a faulty external input is found, the loop is resolved, and the processor instructs the operator to probe another node. If the external inputs are all good, the main processor scans the history table to determine which node in the loop failed first and indicates that the component driving that node is the probable fault.

Claims61

Dependent claims

A method for isolating faults in a loop of a digital circuit, the loop including a plurality of nodes, the method comprising the steps of:

(a) for each node in the loop
i. applying a predetermined sequence of test signals to an input of the digital circuit;
ii. comparing a response of the node to the known correct response of the node to determine if the node response is faulty;
iii. if the node response is faulty, storing information representative of a time of occurrence of the earlier of an actual initial transition of the node and a known correct initial transition of the node;
(b) testing loop entry nodes of the loop to determine if the response of any loop entry node is faulty until a loop entry node having a faulty response is determined;
and
(c) if none of the loop entry nodes are faulty, determining which node corresponds to the earliest of said stored information representative of said initial transitions.

4 more elements

A method for isolating faults in a digital loop of a digital circuit having a plurality of inputs, the digital loop including a plurality of loop nodes, the loop nodes being outputs and/or inputs of logic elements of the digital loop, the digital loop also having at least one loop entry node, the loop entry node being an input to a logic element of digital loop but not being an output of any logic element in the digital loop, said method comprising the steps of:

(a) for each individual loop node
i. applying a sequence of test logic words to the inputs of the digital circuit, each test logic word having a test number representative of the sequential order of occurrence of that test signal;
ii. measuring the response, including the test number of the first transition, of said individual loop node to said applied sequence of test logic signals;
iii. comparing said response to the known correct response for said individual loop node to determine if said individual loop node is faulty;
iv. if said individual loop node is faulty, storing an initial failure number equal to the earlier occurring one of the test number of the first transition of said individual loop node and the test number of the known correct first transition for said individual loop node;
(b) testing the response of each loop entry node to determine if each loop entry node is faulty;
(c) if no loop entry node is faulty, determining from the stored initial failure numbers which loop node has the initial failure number corresponding to to the earliest of said initial failures;
and
(d) displaying information indicating that the logic element which has as an output the one of said loop nodes having said earliest initial failure number is probably defective.

6 more elements

A tester for isolating defects in a digital loop of a digital circuit, said tester comprising:

(a) input means for applying a sequence of input test signals to said digital circuit;
(b) measuring means for measuring the response of each node in said loop to said sequence;
(c) transition detecting means responsive to said measuring means for detecting the initial transition of each node in said loop and determining an input test number of the initial transition of each node in said loop;
(d) comparing means responsive to said measuring means for comparing said responses to the known correct responses for each node in said loop to determine if the response of each node in said loop is faulty;
(e) initial failure number means for producing and storing an initial failure number for each node having a faulty response, the initial failure number for each node having a faulty response which is equal to the smaller of the input test number of the initial transition for that node and the input test number of the known correct initial transition for that node;
(f) testing means responsive to said measuring means for testing the response of each loop entry node to determine if the response of each loop entry node is faulty;
and
(g) detecting means responsive to said initial failure number means for detecting which node has the smallest of said stored initial failure numbers.

5 more elements

A method of isolating defects in a logic circuit having a plurality of input test signals applied thereto and also having a plurality of nodes responsive to the input test signals, said method comprising:

(a) identifying a first one of said nodes having a faulty reponse;
(b) identifying a first logic element having an output connected to said first node;
(c) testing the responses of each input of said first logic element until either a faulty input response is found or all of the input responses are found to be correct;
(d) if all input responses of said first logic element are correct, instructing an operator that the first logic element is probably defective;
(e) if a first input node of said first logic element has a faulty response, identifying a second logic element having an output connected to said first input node and testing the response of each input node of said second logic element until either a faulty input response is found or all of the input response are found to be correct;
wherein, for each input node tested, said testing includes instructing the operator to manually probe that input node to detect its response, and performing a signature analysis on the detected response to determine if the detected response is faulty.

3 more elements

A tester for isolating defects in a logic circuit, said tester comprising in combination:

(a) input means for applying a sequence of input test signals to said logic circuit to produce responses at a plurality of nodes of said logic circuit;
(b) measuring means for measuring said responses of said nodes;
(c) first means responsive to said measuring means for identifying a first one of said nodes having a faulty response;
(d) second means responsive to said first means for identifying a first logic element of said logic circuit, said first logic circuit having an output connected to said first node;
(e) third means responsive to said second means for identifying ones of said nodes connected to the inputs of said first logic element;
(f) instructing means responsive to said third means for automatically instructing an operator to manually probe each one of said input nodes to detect the response of each one of said input nodes until either a faulty input response is found or all of the input responses are found to be correct;
(g) analysis means for performing a signature analysis of the detected responses of each of said nodes to determine if the detected response of each of said nodes is faulty;
(h) signaling means responsive to said analysis means for signaling the operator that said first logic element is defective if all of said input node responses are found to be correct;
and
(i) fourth means responsive to said analysis means for identifying a second logic element having an output connected to one of said inputs having a faulty response, if said one of said inputs if found to have a faulty response.

7 more elements

A method of utilizing a processor-based tester for isolating a faulty logic element in a logic circuit being tested by the tester, the logic circuit including a plurality of logic elements and a plurality of nodes interconnected to form the logic circuit, the tester including a probe for use by an operator for inputting electrical signals from said nodes into the tester, the tester including a memory for storing a test program, an image file, and a response file, the test program defining input test signals to be applied to the logic circuit, the image file containing information descriptive of the interconnections of the logical elements and nodes of the logic circuit, and the response file containing the known correct responses of each node to the test program, the tester having a display unit for displaying messages, a first one of said nodes being faulty, said method comprising the steps of:

(a) identifying a first logic element which has said first node as an output;
(b) testing each of the inputs of said first logic element until either a faulty input of the first logic element is found or until all inputs of the first logic element are determined to be non-faulty;
(c) if all inputs of the first logic element are found to be non-faulty, then displaying an indicator indicating that the first logic element is defective;
and
(d) if a faulty input of the first logic element is found, identifying a second logic element having said faulty input as an output and testing each of the inputs of the second logic element until either a faulty input of the second logic element is found or until all inputs of the second logical element are determined to be non-faulty;
wherein said testing of each one of said input nodes includes the step of displaying an instruction by means of said display unit to instruct an operator to probe said one of said input nodes and further includes the step of probing one of said input nodes in response to said displayed instruction and detecting the response of each of of said input nodes to a sequence of input test signals applied to an input of the logic circuit.

3 more elements

Dependencies are inferred from the claim text.

Method and apparatus for isolating faults in a logic circuit

Life of this patent

Method and apparatus for isolating faults in a logic circuit

Life of this patent

Abstract

Claims61