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US 4,193,037 AGranted
Frequency divider circuit with selectable integer/non-integer division
AssigneeMotorola, Inc.
InventorShikun Kyu
Life of this patent
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Abstract
A divide circuit is provided for dividing an input signal of frequency N by the quantity M+0.5, where N is any positive number and M is an integer. In one embodiment a clock signal operating at a frequency of 3.5 megahertz is divided by 3.5, yielding an output signal of 1 megahertz. Additional logic means may be provided responsive to a control signal for dividing the input signal by the quantity M+1 for a given state of the control signal.
Claims13
A divide circuit comprising:
- an AND-OR-INVERTER comprising first and second AND gates and a first NOR gate responsive to the outputs of said AND gates;
- a first flip-flop responsive to the output of said AND-OR-INVERTER and having first and second transmission gates, said first flip-flop generating outputs A and B;
- a second flip-flop responsive to said output B and having third and fourth transmission gates, said second flip-flop generating an output C;
- a second NOR gate responsive to said output C and generating an output D;
- a third flip-flop responsive to said output D and having fifth and sixth transmission gates, said third flip-flop generating an output E;
- a clock source providing a first clock signal of frequency N to said first, third, and fifth transmission gates, said clock source further providing a second clock signal of frequency N to said second, fourth, and sixth transmission gates, said first and second clock signals being non-overlapping;
- a fourth flip-flop responsive to said outputs A and C and generating an output F and its complement F;
- means coupling said output E to one input of said first AND gate, coupling said complement F to the other input of said first AND gate, coupling said output D to one input of said second AND gate, and coupling said output F to the other input of said second AND gate;
- additional means coupling said outputs B and E to said second NOR gate as additional inputs thereto;
- and
- a third NOR gate resposive to said outputs A and E and generating an output G having a frequency equal to N/(M+0.5, M being a positive integer.
8 more elements
A divide circuit comprising:
- means responsive to an external clock signal of frequency N for generating an output signal of frequency N/(M+0.5), M being a positive integer;
- and
- additional means responsive to an external control signal having first and second states, said divide circuit generating said output signal at frequency N/(M+0.5) when said control signal is in said first state and generating said output signal at frequency N/(M+1) when said control signal in said second state.
A divide circuit comprising:
- a clock source providing first and second clock signals each of frequency N, said first and second clock signals being non-overlapping;
- first logic means responsive to a given transition in said first clock signal for generating a first output having a duration not exceeding three cycles of said first clock signal;
- second logic means responsive to said first and second clock signals for generating a second output M+0.5 cycles of said first clock signal after said first output is generated and having a duration not exceeding three cycles of said first clock signal, M being a positive integer;
- third logic means responsive to the presence of either said first or second outputs for generating a third output, said third output having a frequency equal to N/(M+0.5);
- and
- fourth logic means responsive to a control signal having first and second states, said divide circuit generating said third output at frequency N/(M+0.5) when said control signal is in said first state and generating said third output signal at frequency N/(M+1) when said control signal is in said second state.
3 more elements
Dependencies are inferred from the claim text.