Single slope A/D converter with sample and hold

An analog voltage to digital pulse converter circuit comprising in combination:

• a bistable flip-flop having a first stable state defined as a conversion interval and a second stable state defined as a quiescent interval;
• means for applying a set pulse to said flip-flop to initiate said conversion interval;
• a capacitor;
• means for coupling said capacitor to an analog voltage to be converted during said quiescent interval whereby said capacitor is charged to said analog voltage;
• means for developing an increment of voltage and adding said increment to the charge on said capacitor during said conversion interval, said increment being small with respect to the expected range of analog voltages to be converted;
• means for coupling a constant current load device to discharge said capacitor during said conversion interval, said discharge producing a linear decline in voltage with time;
• means for developing a reference voltage that is greater than zero but less than said increment;
• comparison means having two inputs and an output said inputs coupled to said capacitor and to said reference potential means and said output being coupled to said flip-flop to terminate said conversion interval when said capacitor voltage falls below said reference voltage whereby said conversion interval is linearly proportional to said analog voltage just prior to said initiation of said conversion interval.