US 4,191,924 AGranted

Channel selection apparatus

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorsMasahiro Takeshita, Kazumi Kawashima, Minoru Ueda, Keisuke Yamamoto

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Abstract

A channel selection apparatus comprises a counter, a decoder, a clock pulse generator, and a control circuit for controlling them, and selects a channel by switching a channel selection voltage by selecting a potentiometer. The counter includes a cascade-connected flip-flop such that a trailing edge of an AND output of an output of a flip-flop in one stage and a channel selection count input signal triggers a flip-flop in the following stage. The decoder includes a plurality of output transistors and a plurality of parallel-connected transistor sets with common collectors of each of the transistor sets being connected to a base of a corresponding output transistor and input signals being applied to bases of each of the transistor sets.

Claims18

Dependent claims

A channel selection apparatus comprising:

a tuner having a voltage dependent variable reactance element as a tuning element;
a plurality of potentiometers for presetting channel selection voltages one for each of a plurality of channels, said channel selection voltages being selectively applied to said variable reactance element of said tuner for selecting a disired channel;
a coupling means for coupling selected one of said potentiometers to said turner such that one of said channel selection voltages taken from said selected potentiometer is applied to said variable reactance element of said tuner;
a counter including a plurality of flip-flops and connecting means for cascade-connecting said plurality of flip-flops such that a trailing edge of an AND output of an output of the flip-flop in one stage and a channel selection count input signal triggers the flip-flop of the next stage;
a clock pulse generating circuit for generating clock pulses;
a control circuit responsive to a channel selection control input applied to an input terminal thereof to extract said clock pulses and couple said counter to said clock pulse generating circuit such that said extracted clock pulses are applied to said counter as said count input signal;
a decoder including binary signal input terminals, a plurality of output terminals said decoder being responsive to said binary signal to produce an output at one of said output terminals, a plurality of output transistors connected to said plurality of output terminals, respectively, a plurality of parallel-connected transistor sets, means for coupling the bases of said output transistors to the common collectors of the respective ones of said transistor sets, and means for coupling said binary signal input terminals to the bases of the respective ones of said transistor sets;
a coupling means for coupling said output terminals of said decoder to said potentiometers to select one of said plurality of potentiometers in accordance with the output of said decoder;
and
a switch means connected to said input terminal of said control circuit to apply said channel selection control input to said input terminal.

7 more elements

A channel selection switch comprising;

a tuner having a voltage dependent variable reactance element as a tuning element;
a plurality of potentiometers for presetting channel selection voltages one for each of a plurality of channels, said channel selection voltages being selectively applied to said variable reactance element of said tuner for selecting a desired channel;
a coupling means for coupling selected one of said potentiometers to said tuner such that one of said channel selection voltages taken from said selected potentiometer is applied to said variable reactance element of said tuner;
a counter including a plurality of cascade-connected flip-flops, an input terminal to which channel selection clock pulses to be counted by said flip-flops are applied and a binary output terminal from which a binary signal indicative of the count is taken;
a clock pulses generating circuit for generating clock pulses;
a control circuit responsive to a channel selection control input applied to an input terminal thereof to extract said clock pulses and couple said counter to said clock pulse generating circuit such that said extracted clock pulses are applied to said counter as said count input signal;
a decoder including binary signal input terminals, a plurality of output terminals, said decoder being responsive to said binary signal to produce an output at one of said output terminals, a plurality of output transistors connected to said plurality of output terminals, respectively, a plurality of parallel-connected transistor sets, means for coupling the bases of said output transistors to the common collectors for the respective ones of said transistor sets, and means for coupling said binary signal input terminals to the bases of the respective ones of said transistor sets;
a coupling means for coupling said output terminals of said decoder to said potentiometers to select one of said plurality of potentiometers in accordance with the output of said decoder;
and
a switch means connected to said input terminal of said control circuit to apply said channel selection control input to said input terminal.

7 more elements

Dependencies are inferred from the claim text.