Semiconductor device having two intersecting sub-diodes and transistor-like properties

A semiconductor device comprising in combination:

• a substrate;
• a substantially intrinsic (I) semiconductor layer on the substrate;
• a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode;
• a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path;
• the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials;
• and
• the distance between the first P doped zone and the first N doped zone, and the distance between the second P doped zone and the second N doped zone being shorter than or equal to the average diffusion length of free charge carriers in the base zone located between these doped zones.

A semiconductor device comprising in combination:

• a substrate;
• a substantially intrinsic (I) semiconductor layer on the substrate;
• a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode;
• a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path;
• the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials;
• and
• the distance between the second P doped zone and the second N doped zone being shorter than an average diffusion length of free charge carriers in the base zone, and the distance between the first P doped zone and the first N doped zone being considerably greater than said average diffusion length.

A semiconductor device comprising in combination:

• a substrate;
• a substantially intrinsic (I) semiconductor layer on the substrate;
• a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode;
• a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path;
• the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials;
• at least one further pair comprised of a P doped zone and a N doped zone being provided, the connection lines between the P and N doped zones of each pair intersecting the connection line between the first P doped zone and the first N doped zone;
• and
• the connection lines between the P and N doped zones of each pair intersecting the connection line between the first P doped zone and first N doped zone at right angles thereto.

A semiconductor device comprising in combination:

• a substrate;
• a substantially intrinsic (I) semiconductor layer on the substrate;
• a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode;
• a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path;
• the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials;
• and
• an insulating layer being provided on said semiconductor layer, and on said insulating layer there being arranged a field effect electrode which extends over the base zone.

A semiconductor device comprising in combination:

• a substrate;
• a substantially intrinsic (I) semiconductor layer on the substrate;
• a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductory layer which serves as a base zone so as to form a first PIN diode;
• a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path;
• the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials;
• and
• an input control signal source means being provided in the first external circuit means and an output load means being connected in the second external circuit means for creating an output signal which is an amplification of an input signal of the input control signal source means.