Digital attenuator for compressed PCM signals

A digital attenuator comprising:

• first, second and third pattern shift circuits;
• means for branching an input compressed PCM signal to each of said pattern shift circuits;
• said first pattern shift circuit having means for shifting the branched input PCM signal to the lower side by a predetermined number of bits, from one bit to five bits;
• said second pattern shift circuit having means for shifting the branched input PCM signal to the lower side by a predetermined number of bits, from one bit to five bits, which differ from those in the first pattern shift circuit;
• a first adder for adding the outputs from the first and second pattern shift circuits;
• said third pattern shift circuit having means for shifting the branched input PCM signal to the lower side by a predetermined number of bits, from one bit to five bits, which differ from those in the first and second pattern shift circuits;
• a second adder for adding the output of the first adder with the output from the third pattern shift circuit to provide an attenuated PCM signal;
• and
• a selector for selecting the input PCM signal when no attenuation control signal is applied to the selector, or selecting the attenuated PCM signal when an attenuation control signal is applied to the selector, as the output signal.