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US 4,181,862 AGranted
High speed resettable dynamic counter
AssigneeRCA Corporation
InventorAndrew G. F. Dingwall
Life of this patent
Estimating the term…
Abstract
A counter stage includes a clocked transmission gate which, when turned on, couples the output of the stage back to its input. A resetting circuit is connected to the input of the stage for selectively clamping the input to a fixed voltage level representative of a logic one or a logic zero. The resetting circuit is enabled only when the clocked transmission gate is turned off, whereby no current can flow from, or to, the output via the resetting means. This enables high speed of reset since the input of the stage is then easily discharged (or charged) to the selected fixed level via the resetting circuit.
Claims10
A counter stage in combination with a source of cyclical signals having a first binary significance during a first portion of the cycle and having a second binary significance during a second portion of the cycle, comprising:
- a first section and a second section, one of said first and second sections having an input and an output at which is produced a signal 180.degree. out-of-phase with a signal at its input, and the other one of said first and second sections having an input and an output at which is produced a signal in-phase with a signal at its input;
- a first transmission gate connected between the output of the first section and the input to the second section for, when enabled, coupling the output of the first section to the input of the second section;
- a second transmission gate connected between the output of the second section and the input of the first section for, when enabled, coupling the output of the second section to the input of the first section;
- resetting means coupled to the input of the first section for, when enabled, setting the input of the first section to a predetermined level;
- means for continuously applying said cyclical signals to said first and second transmission gates for enabling said first transmission gate and disabling said second transmission gate during said first portion of each cycle, and for enabling said second transmission gate and disabling said first transmission gate during said second portion of each cycle;
- a terminal adapted to receive a reset signal;
- and
- gating means responsive to said cyclical signals and to said reset signal for enabling said resetting means only during said first portion of each cycle and when a reset signal is present.
5 more elements
A high speed counter comprising:
- a source of cyclical input signals to be counted, said input signals having a first and a second portion per cycle;
- a resettable counter stage for counting said input signals and producing output signals responsive to said input signals including:
- (a) a master section and a slave section;
- (b) a first transmission gate connected between the output of the master section and the input to the slave section;
- (c) a second transmission gate connected between the output of the slave section and the input of the master section;
- and (d) means applying said input signals to said first and second transmission gates for enabling said first transmission gate and disabling said second transmission gate during said first portion and for enabling said second transmission gate and disabling said first transmission gate during said second portion of each input signal cycle;
- K-1 cascaded counter stages for counting, when enabled, the output signals of said resettable stage where K is an integer greater than 1;
- and
- resetting means coupled to the input of said master section responsive to a predetermined state of said K-1 counter stages and of said resettable stage, and to said input signal being in said first portion of its cycle for resetting the master section of said first stage while said second transmission gate is disabled.
6 more elements
A high speed counter comprising:
- a source of cyclical input signals to be counted, said input signals having a first and a second portion per cycle;
- a resettable counter stage for counting said input signals and producing output signals responsive to said input signals including:
- (a) first and second sections, each section having an input and an output;
- one of said first and second sections having an output at which is produced a signal 180.degree. out-of-phase with a signal applied to its input, and the other one of said first and second sections having an output at which is produced a signal in-phase with a signal applied to its input;
- and
- (b) means responsive to said cyclical input signals for coupling said output of said first stage to said input of said second stage and decoupling the output of said second stage from the input of said first stage during said first portion of each cycle and for coupling said output of said second stage to said input of said first stage and decoupling the output of said first stage from the input of said second stage during said second portion of each cycle;
- K-1 cascaded counter stages for counting, when enabled, the output signals of said resettable stage where K is an integer greater than 1;
- and
- resetting means coupled to the input of said first section, responsive to a predetermined state of said K-1 counter stages and of said resettable stage, and to said input signal being in said first portion of its cycle for resetting said first section of said first stage while said output of said second stage is decoupled from said input of said first stage and while said second section is already in the state in which it would be placed by the transfer of the output of the first section to the input of the second section.
6 more elements
Dependencies are inferred from the claim text.