PROM electrically written by solid phase epitaxy
AssigneeHarris Corporation
InventorRonald G. Neale
Life of this patent
Estimating the term…
Abstract
A memory cell, having a doped amorphous silicon layer, is formed on a thin layer of silicon alloy which is on a single crystal silicon substrate. The cell is programmed by applying a voltage between a surface contact and the substrate to cause a crystal column to form in the amorphous layer between the substrate and the contact by solid-phase epitaxial growth. A diode is formed between the contact and the substrate by the selection of impurity levels and conductivity type of the amorphous layer and substrate and the selection of the silicon alloy. The cross-sectional area of the column is selectable to provide a multi storage level cell.
Claims36
A method of producing a PROM element comprising:
- forming a palladium silicide layer on a single crystal silicon substrate;
- forming a layer of amorphous silicon on said palladium silicide layer;
- forming a contact layer on said amorphous layer;
- and
- applying programming voltage across said contact and said substrate of sufficient magnitude and duration to cause solid-phase epitaxial growth in said amorphous layer of a column of single crystal silicon extending between said substrate and said contact layer.
A method of fabricating a read only memory comprising:
- forming a plurality of discrete regions of palladium silicide on a single crystal silicon substrate;
- forming a layer of amorphous silicon on each of said discrete regions of palladium silicide;
- forming a contact layer on each of said amorphous silicon layers;
- creating a current between said substrate and selected contacts of a sufficient magnitude and duration to cause a column of single crystal silicon to epitaxially grow through said amorphous layer between said substrate and said selected contacts.
A semiconductor structure comprising:
- a substrate of single crystal silicon;
- a first layer of palladium silicide on said substrate;
- a second layer of doped amorphous silicon on said first layer;
- a third layer of contact material on said second layer;
- a column of doped single crystal silicon on said substrate surrounded laterally by said first and second layers;
- and
- a fourth layer of palladium silicide between said column and said third layer.
In a programmable read only memory including a substrate and a plurality of storage locations formed on said substrate having either a first or second logic state, including at least one storage location in each of said logic states;
- each storage location having a first logic state comprising a first layer of palladium silicide on said substrate, a second layer of amorphous silicon on said first layer, and a third layer of contact material on said second layer;
- and
- each storage location having a second logic state comprising a first, second and third layer as each of said storage locations having a first logic state, a column of doped single crystal silicon extending between said substrate and said third layer and laterally surrounded by said first and second layers, and a fourth layer of palladium silicide between said column and said third layer.
A method of programming a programable read only memory having a crystalline substrate of a semiconductor material, and a plurality of spaced storage locations on said substrate, each including an alloy layer of a metal and said semiconductor material on said substrate, an amorphous layer of said semiconductor material on said alloy layer and a contact layer on said amorphous layer comprising:
- applying a voltage across said substrate and said contact layer for the location to be programmed of a sufficient magnitude and duration to cause solid-phase epitaxial growth in said amorphous layer of a crystalline column of said semiconductor material extending between said substrate and said contact layer.
A method of fabricating and programming a PROM element comprising:
- providing a layer of single crystal semiconductor material;
- forming an alloy layer of a metal and said semiconductor material on said single crystal layer;
- forming an amorphous layer of said semiconductor material on said alloy layer;
- forming a contact layer on said amorphous layer;
- and
- applying a programming voltage across said contact layer and said single crystal layer of sufficient magnitude and duration to cause solid-phase epitaxial growth in said amorphous layer of a column of single crystal semiconductor extending between said single crystal layer and said contact layer.
A semiconductor structure comprising:
- a layer of single crystal semiconductor material;
- a alloy layer of a metal and said semiconductor material;
- a doped amorphous layer of said semiconductor material on said alloy layer;
- a contact layer of contact material on said amorphous layer;
- a doped single crystal column of said semiconductor material on said single crystal layer surrounded laterally by said alloy and amorphous layers;
- and
- a layer of said alloy between said column and said contact layer.
In a programmable read only memory including a substrate of a semiconductor material and a plurality of storage locations formed on said substrate having either a first or second logic state, including at least one storage location in each of said logic states;
- each storage location having a first logic state comprising a first layer of an alloy of metal and said semiconductor material on said substrate, a second layer of amorphous form of said semiconductor material on said first layer, and a third layer of contact material on said second layer;
- and
- each storage location having a second logic state comprising a first, second and third layer as each of said storage locations having a first logic state, a column of doped single crystal form of said semiconductor material extending between said substrate and said third layer and laterally surrounded by said first and second layers, and a fourth layer of said alloy between said column and said third layer.
Dependencies are inferred from the claim text.