Programmable controller with programmable I/O scan rate

A programmable controller for controlling operating devices on a machine, the combination comprising:

• memory means which stores at selected memory locations a plurality of controller instructions which comprise a control program, a plurality of multi-bit status words which comprise an I/O image table, and a set of machine instructions;
• an address bus connected to said memory means to couple address data to said memory means which selects memory locations therein;
• a multi-lead data bus connected to said memory means to couple data to and from said memory means;
• an I/O interface rack coupled to said address bus and said data bus, said I/O interface rack including input and output circuits for coupling the programmable controller to sensing devices and operating devices on the machine to be controlled;
• processor means connected to said address bus and said multi-lead data bus and being operable in response to the execution of a first selected set of said machine instructions to sequentially read said controller instructions out of said memory means onto said multi-lead data bus, operable in response to the execution of a second selected set of said machine instructions to read selected status words out of said I/O image table onto said multi-lead data bus, operable in response to the execution of a third selected set of said machine instructions to generate status words on said multi-lead data bus and write them into selected memory lines of said I/O image table, and operable in response to the execution of a fourth selected set of said machine instructions to read status words out of said I/O image table and couple them to said I/O interface rack through said multi-lead data bus;
• a Boolean processor coupled to said multi-lead data bus and said processor means, said Boolean processor being responsive to control signals generated by said processor means to perform a set of single-bit calculations on selected status bits in said I/O image table which are coupled to it through said multi-lead data bus, and being responsive to other control signals generated by said processor means to generate a single-bit result on a selected lead in said multi-lead data bus, which single-bit result is coupled to said I/O image table through said multi-lead data bus,
• wherein said processor means is responsive to input immediate control program instructions read from said memory means to select and execute a fifth set of said machine instructions which direct the processor means to input a status word from sensing devices coupled to said I/O interface rack, to couple said status word through said multi-lead data bus to said Boolean processor, and to couple said status word to said I/O image table through said multi-lead data bus;
• and wherein said processor means is responsive to output immediate control program instructions read from said memory means to select and execute a sixth set of said machine instructions which direct the processor means to couple said single-bit result generated by said Boolean processor through said multi-lead data bus to an operating device which is coupled to said I/O interface rack.