Digital data communication adapter
AssigneeNCR Corporation
InventorsBipin D. Parikh, Haresh C. Patnaik, Bhagubhai K. Patel, Prabodh M. Dharia, John J. Kurtz, Alfred D. Jenkins, Prakash Y. Mahajan
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AssigneeNCR Corporation
InventorsBipin D. Parikh, Haresh C. Patnaik, Bhagubhai K. Patel, Prabodh M. Dharia, John J. Kurtz, Alfred D. Jenkins, Prakash Y. Mahajan
Estimating the term…
Communications between processor terminals are carried out through the use of communication adapters. Each adapter receives selected control signals for transmitting or receiving data over a serial communication link to or from a remote terminal. The transmission portion of an adapter includes pretransmission control circuitry which receives control signals and stores transmission control signals which are used to control the format and serial transmission of a frame of data to a remote terminal. Each frame of data is begun and terminated with a uniquely encoded flag byte. Following the first flag byte are successive address and control fields. An optional information field may follow the control field and may include encoded information designating a dynamic change in the byte size of the data. Immediately following the information field, a frame check sequence field, generated in accordance with the contents of each of the address, control, and information field, is transmitted, followed by a frame terminating flag byte. In order to enable the adapter to receive a serial data stream from a remote terminal and couple this received data to its assoicated processor, the adpater includes pre-reception control and direct memory access control circuitry coupled over the common control bus to the common control module and its associated memory. Upon completely disassembling a frame, the adapter generates appropriate status signals and an interrupt is supplied to the common control.
A method of controlling the transmission and reception of a frame of data in serial format, from a first processing terminal to at least one second processing terminal, respectively, comprising the steps of:
A method of controlling the transmission and reception of a frame of data in serial format, from a first processing terminal to at least one second processing terminal, respectively, comprising the steps of:
A method of controlling the transmission and reception of a frame of data in serial format, from a first processing terminal to at least one second processing terminal, respectively, comprising the steps of:
A method of controlling the transmission and reception of a frame of data in serial format, from a first processing terminal to at least one second processing terminal, respectively, comprising the steps of:
A data communication system for controlling the transmission and reception of a frame of data in serial format, from a first processing terminal whereat data to be transmitted is read out from a selectively addressable memory, said frame being comprised of a sequence of signal containing address, control, and data information fields, to at least one second processing terminal whereat received data is written into a selectively addressable memory, comprising:
A data communication system for controlling the transmission and reception of a frame of data in serial format, from a first processing terminal whereat data to be transmitted is read out from a selectively addressable memory, said frame being comprised of a sequence of signals containing address, control, and data information fields, to at least one second processing terminal whereat received data is written into a selectively addressable memory, comprising:
A data communication system for controlling the transmission and reception of a frame of data in serial format, from a first processing terminal whereat data to be transmitted is read out from a selectively addressable memory, said frame being comprised of a sequence of signals containing address, control, and data information fields, to at least one second processing terminal whereat received data is written into a selectively addressable memory, comprising:
A data communication system for controlling the transmission and reception of a frame of data in serial format, from a first processing terminal whereat data to be transmitted is read out from a selectively addressable memory, said frame being comprised of a sequence of signals containing address, control, and data information fields, to at least one secoond processing terminal whereat received data is written into a selectively addressable memory, comprising:
A method of controlling the transmission of a frame of data in serial format from a first processing terminal to at least one second processing terminal comprising the steps of:
A data communication system for controlling the transmission of a frame of data in serial format from a first processing terminal to at least one second processing terminal, said frame being comprised of a sequence of signals containing address, control, and data information fields, comprising:
Dependencies are inferred from the claim text.