Digital control system with Boolean processor

A programmable controller comprising:

• a random access memory which stores a plurality of macro-instructions which comprise a control program, each of said macro-instructions including a selected one of a plurality of types of operation codes;
• a read-only memory which stores a first set of machine instructions which comprise a macro-instruction decoding routine, and a plurality of sets of machine instructions which comprise macro-instruction execution routines, there being a unique macro-instruction execution routine associated with each type of macro-instruction operation code;
• an address bus connected to said random access memory and said read-only memory to select a line therein;
• a data bus connected to said random access memory to couple data to and from said random access memory and connected to said read-only memory to couple data from said read-only memory;
• an I/O interface rack coupled to said address bus and said data bus, said I/O interface rack including input and output circuits for coupling the data bus to sensing devices and operating devices on a machine to be controlled;
• and
• a microprocessor for executing machine instructions, said microprocessor being connected to said data bus and said address bus and having a program counter which stores the memory address of a machine instruction stored in said read-only memory and a stack pointer register which stores the address of a macro-instruction stored in said random access memory, said microprocessor being responsive to selected machine instructions in said macro-instruction decoding routine to read out of said random access memory the macro-instruction addressed by said stack pointer register and being responsive to further selected machine instructions in said macro-instruction decoding routine and the operation code in the macro-instruction read from said random access memory to load the starting address of the macro-instruction execution routine which is associated with said operation code into said program counter.

A programmable controller comprising:

• a memory which stores a plurality of control instructions which comprise a control program, each of said control instructions including an operation code and selected ones of said control instructions including an associated bit pointer;
• a microprocessor connected to said memory through an address bus and a multi-lead data bus, said microprocessor being operable to sequentially read said control instructions out of said memory onto said data bus;
• and
• a Boolean processor which comprises:
• a. means coupled to said data bus for decoding selected ones of said operation codes,
• b. bit selector means having inputs connected to said data bus and being responsive to the bit pointer in selected ones of said control instructions read from said memory to selectively couple the logic state on one of said data bus leads to a bit selector output terminal,
• c. main decision storage means having an input terminal coupled to said bit selector output terminal, an enable terminal connected to said decoding means and an output terminal, said main decision storage means being responsive to selected decoded operation codes to store a logic state indicative of the logic state of said bit selector output terminal, and
• d. second bit selector means having an input terminal coupled to said main decision storage means output terminal, having a plurality of output terminals coupled to respective leads in said multi-lead data bus, and having an enable terminal coupled to said decoding means, said second bit selector means being responsive to selected decoded operation codes and their associated bit pointer to couple the logic state of said main decision storage means to a selected one of said data bus leads;
• and
• in which said Boolean processor includes gate means having one input coupled to said main decision storage means, a second input coupled to said microprocessor, and an output terminal connected to one lead in said data bus, said microprocessor being operable to enable said gate means to couple the logic state of said main decision storage means to said one data bus lead.

A digital control system comprising:

• memory means which stores on selected memory lines a plurality of controller instructions which comprise a control program, a plurality of multi-bit status words which comprise an I/O image table, and a set of machine instructions;
• an address bus connected to said memory means to select a memory line therein;
• a multi-lead data bus connected to said memory means to couple data to and from said memory means;
• an I/O interface rack coupled to said address bus and said data bus, said I/O interface rack including input and output circuits for coupling the digital control system to sensing devices and operating devices on a machine to be controlled;
• processor means responsive to selected machine instructions to sequentially read said controller instructions out of said memory means, responsive to other selected machine instructions to read selected status words out of said I/O image table, responsive to other selected machine instructions to write status words into selected memory lines of said I/O image table, and responsive to other machine instructions to couple status words between said I/O image table and said I/O interface rack;
• and
• a Boolean processor coupled to said data bus and said processor means, said Boolean processor being responsive to control signals from said processor means to perform a set of single-bit calculations on selected status bits in said I/O image table which are coupled to it through said multi-lead data bus, and which are to generate a single-bit result on a selected lead in said multi-lead data bus, which result is coupled to said I/O image table.