Clock pulse generator with selective pulse delay and pulse width control

Clock pulse delay and pulse width adjusting apparatus for adjusting pulse delay and pulse width of a series of repetitive clock pulses emanating from a source of clock pulses in a programmed computer system, the improvement comprising:

• a delay line connected to receive said series of repetitive clock pulses, and having a set of outputs for providing a set of delayed clock pulses for each received clock pulse,
• pulse delay selector means connected to said delay line to receive said set of delayed clock pulses and selectively operable to pass only one delayed pulse of said set of delayed pulses,
• pulse width selector means connected to said delay line to receive said set of delayed clock pulses and selectively operable to pass only one delayed pulse of said set of delayed pulses,
• pulse delay scan ring means settable under program control for controlling selective operation of said pulse delay selector means,
• pulse width scan ring means settable under program control, for controlling selective operation of said pulse width selector means,
• first dither-delay circuit means for delaying pulses from said pulse delay selector means less than the amount of delay between pulses of said set of delayed pulses,
• second dither-delay circuit means for delaying pulses from said pulse width selector means less than the amount of delay between pulses of said set of delayed pulses,
• logic circuit means for forming adjusted pulses from pulses passed by said pulse delay and said pulse width selector means and said first and second dither-delay circuit means,
• first switch means connected to receive pulses from said pulse delay selector means and from said first dither-delay circuit means and selectively operable under control of said pulse delay scan ring means to pass either the pulse from said pulse delay selector means or the pulse from said first dither-delay circuit means to said logic circuit means, and
• second switch means connected to receive pulses from said pulse width selector means and from said second dither-delay circuit means and selectively operable under control of said pulse width scan ring means to pass either the pulse from said pulse width selector means or the pulse from said second dither-delay circuit means to said logic circuit means.

Clock pulse generating apparatus for a stored program computer system, including means for providing a series of repetitive clock pulses, the improvement comprising:

• coarse pulse delay and pulse width adjusting means for adjusting the pulse delay and pulse width of said series of repetitive clock pulses, said coarse pulse delay and pulse width adjusting means comprising:
• coarse delay circuit means for providing a set of delayed pulses from each pulse of said series of repetitive pulses,
• coarse pulse delay selector means connected to receive said set of delayed pulses and having a number of selectively operable control elements equal in number to the number of delayed pulses in said set of delayed pulses, each control element having an input connected to receive one delayed pulse of said set of delayed pulses, an output and a control input which upon being energized passes said one delayed pulse to said output, said output of each control element being commonly connected to an output of said pulse delay selector means,
• coarse pulse width selector means connected to receive said set of delayed pulses and having a number of selectively operable control elements equal in number to the number of delayed pulses in said set of delayed pulses, each control element having an input connected to receive one delayed pulse of said set of delayed pulses, an output and a control input which upon being energized passes said one delayed pulse to said output, said output of each control element being commonly connected to an output of said pulse width selected means,
• coarse pulse delay scan ring means settable under program control for controlling selective energization of said control inputs of the control elements in said coarse pulse delay selector means, p1 coarse pulse width scan ring means settable under program control for controlling selective energization of said control inputs of said control elements in said coarse pulse width selector means, and
• coarse logic circuit means for forming adjusted clock pulses from pulses passed by said coarse pulse delay and said coarse pulse width selector means,
• fine pulse delay and pulse width adjustments for finely adjusting the pulse delay and pulse width of said series of repetitive clock pulses, said fine pulse delay and pulse width adjusting means comprising:
• fine delay circuit means for providing a set of delayed pulses from each adjusted pulse formed by said logic circuit means of said coarse pulse delay and pulse width adjusting means,
• fine pulse delay selector means connected to receive said set of delayed pulses and having a number of selectively operable control elements equal in number to the number of delayed pulses in said set of delayed pulses, each control element having an input connected to receive one delayed pulse of said set of delayed pulses, an output and a control input which upon being energized passes said one delayed pulse to said output, said output of each control element being commonly connected to an output of said pulse delay selector means,
• fine pulse width selector means connected to receive said set of delayed pulses and having a number of selectively operable control elements equal in number to the number of delayed pulses in said set of delayed pulses, each control element having an input connected to receive one delayed pulse of said set of delayed pulses, an output and a control input which upon being energized passes said one delayed pulse to said output, said output of each control element being commonly connected to an output of said pulse width selector means,
• fine pulse delay scan ring means settable under program control for controlling selective energization of said control inputs of said control elements in said fine pulse delay selector means,
• fine pulse width scan ring means settable under program control for controlling selective energization of said control inputs of said control elements in said fine pulse width selector means, and
• fine logic circuit means for forming adjusted pulses from pulses passed by said fine pulse delay and said fine pulse width selector means.