Programmable divider

For use in a receiver having a phase-locked loop including an electrically controllable local oscillator having a range of output frequencies offset from the range of receiver input frequencies by a fixed offset frequency, a reference frequency source, and a phase detector circuit for comparing the output of the reference frequency source with a divided-down output from the electrically controllable local oscillator;

• a programmable divider for generating the divided-down output comprising
• counter circuit means operable to count through a recurring sequence of counts in response to clock pulses applied thereto and having an output connection coupled to the phase detector circuit;
• counter control means coupled to the counter circuit means comprising
• means for applying clock pulses to the counter circuit means at a rate dependent upon the output from the electrically controllable local oscillator,
• timing means for providing a variable time delay period, said timing means initiating a variable time delay period in response to the occurrence of a first predetermined count in the counter circuit means, and producing an indication upon termination of the variable time delay period, the duration of the time delay period determining the tuned input frequency of the receiver, and
• loading means coupled to the timing means for loading a second predetermined count into the counter circuit means in response to an indication from the timing means upon termination of said variable time delay period,
• the duration of the time delay period initiated by the timing means being less than the time period required for the counter circuit means to count from said first predetermined count to said second predetermined count in response to clock pulses applied thereto;
• said counter circuit means being operable to apply an output pulse to the phase detector circuit in response to the occurrence of a third predetermined count in the counter circuit means.