Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands

Microprogrammable apparatus for performing an arithmetic operation upon a pair of operands, each operand including first and second portions, said apparatus comprising:

• a cycled addressable control store including a plurality of storage locations for storing a corresponding number of microinstruction words, each including a number of control fields, one of said number of control fields including a split control bit coded to specify the physical organization of said apparatus during said performing of an arithmetic operation upon said pair of operands;
• output register means coupled to said control store for storing a microinstruction word read out during a cycle of operation;
• and,
• addressing means coupled to said control store for applying an address for referencing one of said plurality of storage locations during said cycle of operation;
• a first number of multibit microprocessor chips connected to operate in tandem for processing signals corresponding to said first portions of said operands;
• a second number of multibit microprocessor chips connected to operate in tandem for processing signals corresponding to said second portions of said operands;
• each chip of said first and second numbers of chips including:
• an arithmetic and logic unit section;
• a multibit addressable random access memory section connected to said arithmetic logic unit section, said memory section having a plurality of multibit storage locations;
• and,
• a multibit random access memory shift register and multiplexer section;
• and,
• multiplexer control circuit means coupled to a predetermined one of said chips included within said first and second numbers of chips, said control circuit means being coupled to said output register and operative in response to said split control bit of each microinstruction word read out from said control store during said each cycle of operation to selectively interconnect said first and second numbers of chips for operation upon said first and second operand portions as a single operand or as separate operands in accordance with said coding of said split control bit.

A microprogram controlled apparatus for performing arithmetic operations upon a pair of floating point operands, each operand including a mantissa portion and an exponent portion having a plurality of hexidecimal coded digits, said apparatus comprising:

• a cycled addressable control store including a plurality of storage locations for storing a corresponding number of microinstruction words, each including a plurality of control fields one of which includes a split bit coded to indicate interconnection characteristics of said apparatus;
• output register means coupled to said control store for storing a microinstruction word read out during a cycle of operation of said control store;
• and,
• addressing means coupled to control store for applying an address for referencing one of said plurality of storage locations during said cycle of operation;
• first and second numbers of multibit microprocessor chips connected to operate in tandem for processing the digits of said mantissa portions and said exponent portions respectively, each chip having a number of terminals and including:
• an arithmetic logic unit section having first and second sets of input terminals for receiving first and second operands respectively corresponding to said mantissa and exponent portions;
• a multibit addressable random access memory section connected to said arithmetic logic unit section, each said memory section having a plurality of digit storage locations;
• a multibit random access memory shift and multiplexer section connected to said random access memory section and to first and second ones of said number of input terminals;
• and,
• conductor means connecting said first and second terminals on each of said chips to the second and first terminals respectively for a next succeeding and a preceding one of said chips for enabling the shifting of said mantissa and exponent digits by one bit position in a predetermined direction during said cycle of operation;
• and,
• control circuit means coupled to said first and second terminals of a predetermined one of said chips included within each of said numbers, said control circuit means being coupled to said output register and operative in response to each microinstruction word read out from said control store during each cycle to selectively interconnect said numbers of chips for operation as two independent sections and as a single section in accordance with coding of said split bit as required for performing said arithmetic operation upon said pair of operands.