Framing and elastic store circuit apparatus

Frame detection apparatus for detecting frame bits occurring every n serial logic bits where n is an integer comprising, in combination:

• memory means for storing logic bits having 2n logic bit locations with 2n/S addressable word locations with each word being S bits long;
• 2n/S modulo address counter means, connected to said memory means, for sequentially addressing said memory means on a repeating basis;
• data supply means for supplying serial data wherein synchronizing bits occur every n received logic bits;
• initialization means, connected to said memory means, for initializing the apparatus by inserting a candidate bit of a given logic value in said memory means for each of n logic bits;
• logic means, connected to said data supply means and said memory means, for comparing logic bits stored n bits of time earlier with presently received logic bits, for generating disabling candidate bits of a second logic value different from said given logic value on the first occurrence of a negative comparison and for readjusting the location of a logic bit and its associated candidate bit within an addressed word location upon each comparison;
• and
• means for providing an output from said apparatus when only one candidate remains to indicate the framing bit.

The method of detecting framing logic bits in a serial stream of logic bits wherein a framing bit occurs every n consecutive logic bits where n is an integer comprising the steps of:

• filling n candidate locations in an electronic memory with logic bits of a given logic value for initialization of a framing sequence;
• addressing data bit locations in the memory on a repeating sequence basis;
• initially storing n logic bits, where n is an integer greater than 1, from the stream, in locations in said electronic memory wherein each one is retrieved with its corresponding candidate bit in the addressing sequence;
• comparing each presently received bit with the bit received and stored n bits earlier;
• changing the logic value of the candidate bit if the comparison is negative;
• storing the most recently received logic bit from the stream along with its associated candidate bit;
• and
• providing an output indicating frame detection when all but one candidate bit has been changed from the initialized logic value.

Apparatus for detecting framing logic bits in a serial bit stream of logic bits wherein a framing bit occurs every n consecutive logic bits where n is an integer comprising, in combination:

• memory means for storing logic bits including address means for receiving addresses, data bit input means for inputting data and data bit output means for outputting data;
• first means, connected to said memory means, for filling n candidate locations in said memory means with logic bits of a given logic value for initializing a framing sequence in the apparatus;
• second means, connected to said address means of said memory means, for providing data bit addresses of locations in the memory means on a repeating sequence basis;
• third means for supplying a stream of data bits including framing bits;
• fourth means, connected to said data input means of said memory means, for initially storing n logic bits from the stream in locations wherein each of the n logic bits is retrieved with its corresponding candidate bit in the address sequence;
• fifth means, connected to said data output means of said memory means and to said third means, for comparing each bit from said third means with the bit received n bits earlier and stored in said memory means;
• sixth means, connected to said fifth means, for changing the logic value of the candidate bit if the comparison by said fifth means is negative;
• seventh means, connected to said fifth and sixth means, for storing the most recently received data bit from said third means along with its associated candidate bit;
• and
• means, connected to said sixth named means, for providing an output indicating frame detection when all but one candidate bit has been changed from the initialized logic value.

Combination elastic store and framing apparatus comprising, in combination:

• random access memory means for storing logic bits;
• address means connected to said memory means for supplying read and write addresses thereto;
• first logic means, including framing bit counter means, connected to said memory means and said address means, for establishing the framing bit in a series of consecutively applied incoming logic bits and utilizing the memory means in a first function by, (1) comparing all incoming bits with those stored n bits earlier in said memory means where n is an integer and greater than "1", (2) storing a logic "1" in said memory means in a location, previously initialized with a logic "0," if the comparison is negative, (3) counting the number of consecutively occurring logic "1"s with said framing bit counter means until n-1 logic "1"s are counted;
• and (4) establishing framing using the nth count of the counter as a framing bit position indicator where the framing bit occurs every nth incoming logic bit;
• and
• second logic means connected to said memory means and said address means for storing incoming data bits in said memory means in an elastic store second function in accordance with write addresses and later outputting data bits from said memory means in accordance with read addresses, after framing has been established, for synchronizing incoming data to a local clock.