Signal processing apparatus

Signal processing apparatus comprising

• a plurality of capacitive elements arranged in a two-dimensional matrix of rows and columns, each capacitive element including a first capacitor having a common electrode and a first electrode and a second capacitor having a common electrode and a second electrode, said common electrodes being connected together, each capacitive element providing a respective fixed weighting coefficient of a two-dimensional matrix of fixed weighting coefficients, each fixed weighting coefficient having a magnitude equal to the difference in capacitance of the first and second capacitors of a respective capacitive element and having a sign dependent on the relative magnitude of the capacitances of the first and second capacitors of a respective capacitive element,
• a plurality of column lines,
• the common electrodes of the capacitive elements in each column of capacitive elements being connected to a respective column line,
• a plurality of pairs of row lines, each pair including a positive line and a negative line,
• the first electrodes of the capacitive elements in each row being connected to the positive line of a respective pair of row lines,
• the second electrodes of the capacitive elements in each row being connected to the negative line of a respective pair of row lines,
• first means during a first interval of time for setting each of said positive row lines to a respective first potential of a plurality of first potentials and each of said negative row lines to a respective second potential of a plurality of second potentials while connecting each of said column lines to a respective third potential of a plurality of third potentials thereby to charge said capacitive elements,
• second means during a second interval of time for increasing the potential of each of said positive row lines by an amount equal to a respective one of a plurality of analog input voltages and for decreasing the potential of each of said negative row lines by an amount equal to a respective one of said analog input voltages, whereby an output signal is produced on each of said column lines, said output signal being proportional to the algebraic sum of a plurality of partial outputs, each partial output being porportional to the product of the fixed weighting coefficient of a respective capacitive element and a respective analog input voltage.