Cascade charge coupled delay line device for compound delays
AssigneeBoard of Trustees of the Leland Stanford Jr. Unv.
InventorsJohn D. Shott, Roger D. Melen, James D. Meindl
Life of this patent
Estimating the term…
Abstract
A cascade charge coupled delay circuit including a plurality of serial delay line sections formed on a single semiconducter wafer, said delay line sections being directly coupled to one another through the wafer and means for independently clocking each section of said lines.
Claims11
A cascade charge coupled circuit including a plurality of charge coupled delay line sections each including a plurality of charge coupled delay lines of different length formed on a single semiconductor wafer and each delay line directly serially coupled to one another through said wafer and means connected to each said delay line sections for applying independent clocking signals thereto.
A cascade charge coupled circuit including a plurality of adjacent charge coupled delay circuits formed on a single semiconductor wafer disposed parallel to one another, each of said delay circuits including a plurality of charge coupled delay line sections serially coupled to one another through said wafer, at least some of the delay circuits having sections of different length, and means connected to each of said serially coupled sections of adjacent circuits of said plurality of charge coupled delay line circuits to independently control the transfer of charge along each of the sections of adjacent delay line circuits.
A cascade charge coupled circuit including a plurality of adjacent charge coupled delay circuits formed on a single semiconductor wafer and disposed parallel to one another, each of said circuits including at least two charge coupled delay line sections serially connected to one another through said wafer with sections of adjacent circuits being of different lengths, means connected to each of said serially coupled sections of adjacent circuits of said plurality of charge coupled delay line circuits to independently control the transfer of charge along each of the sections of adjacent delay line circuits.
An acoustic imaging system including a plurality of adjacent acoustic transducers, a plurality of charge coupled delay circuits one connected to each of said transducers, said plurality of charge coupled delay circuits formed adjacent and parallel to one another on a single semiconductor wafer, each of said circuits including a plurality of charge coupled delay line sections serially coupled to one another through said wafer and means connected to adjacent sections of said plurality of adjacent charge coupled delay circuits for independently controlling the transfer of charge along adjacent sections of each of said charge coupled delay circuits.
Dependencies are inferred from the claim text.