Fail-safe timing circuit

A fail-safe time element relay comprising, a switching means selectively connecting a source of d.c. voltage to a voltage regulating means, said voltage regulating means supplying regulated voltage to a signal generating means, said signal generating means producing a.c. signals which are fed to an amplifying means, said amplifying means supplying amplified a.c. signals to a rectifying means, said rectifying means rectifying said amplified a.c. signals into a first and a second d.c. voltage, a pulse generating means for supplying signal pulses to a triggering means, said first d.c. voltage which is safe against increasing connected to a timing circuit means for storing a charge, said second d.c. voltage supplying operating potential to an amplifier, said triggering means sampling the amount of stored charge, in a manner which is safe against any failure causing an increase in the charge and which safely removes the charge upon the removal of the source of d.c. voltage, and causing said amplifier to produce amplified pulses, a rectifier for rectifying said amplifier pulses and causing an oscillating level detecting means to produce a.c. oscillations when the amplified rectified pulses reach a predetermined level, an output amplifying means for amplifying said a.c. oscillations, a voltage doubler for rectifying said amplified a.c. oscillations and for energizing an output device a predetermined time after said switching means connects said voltage regulating means to the source of d.c. voltage.