Semiconductor integrated flip-flop circuit device including merged bipolar and field effect transistors

A semiconductor integrated circuit device including at least one register cell formed in a monolithic semiconductor wafer which comprises a semiconductor substrate of a first conductivity type and a semiconductor layer of said first conductivity type disposed on said semiconductor substrate, the register cell including a master flip-flop circuit clocked by a first clock signal, and a slave flip-flop circuit inputted with the outputs of said master flip-flop circuit and clocked by a second clock signal of opposite phase to said first clock signal, each of said master and slave flip-flop circuits comprising:

• a first and a second bipolar transistor each having a base, a first and a second collector and an emitter;
• and
• a first and a second field effect transistor each having a drain, a gate and a source,
• the sources of both said first and second field effect transistors being merged in a first semiconductor region having a second conductivity type opposite to said first conductivity type and disposed in said semiconductor layer,
• the drain of said first field effect transistor and the base of said first bipolar transistor both being merged in a second semiconductor region of said second conductivity type disposed in said semiconductor layer,
• the drain of said second field effect transistor and the base of said second bipolar transistor both being merged in a third semiconductor region of said second conductivity type disposed in said semiconductor layer,
• the emitters of both said first and second bipolar transistors being merged in said semiconductor substrate,
• the first and second collectors of said first bipolar transistor being semiconductor regions of said first conductivity type disposed in said second semiconductor region, respectively,
• the first and second collectors of said second bipolar transistor being semiconductor regions of said first conductivity type disposed in said third semiconductor region, respectively,
• all of said first, second and third semiconductor regions being located adjacent to each other with no isolation layer intervening therebetween,
• the first collectors of said first and second bipolar transistors being connected to the drains of said second and first field effect transistors, respectively,
• the first clock signal being applied to both the gates of said first and second field effect transistors of said master flip-flop circuit,
• the second clock signal being applied to both the gates of said first and second field effect transistors of said slave flip-flop circuit,
• the second collectors of said first and second bipolar transistors of said master flip-flop circuit being connected to the first collectors of said first and second bipolar transistors of said slave flip-flop circuit, respectively.