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AssigneeThomson-CSF
InventorsRaymond Henry, Jean-Victor Bouvet
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A process intended for avoiding the "flip chip bonding" technique, well known for planar diodes, is provided. It is further applicable to mesa diodes and planar transistors. It comprises an essential step: the lapping of the substrate up to reduce its thickness to the same order of magnitude as the upper active layer of a semiconductor device, thus facilitating the cooling of the device through the substrate towards a heat sink. This essential step is made possible by virtue of a preliminary bonding on the upper layer of the semiconductor device of a block of silicon. According to a first alternative of the invention the block is finally eliminated and the device is a conventional one with a very thin substrate. According to a second alternative of the invention, the block is retained and lapped after addition of the heat sink, then metalized to provide a secondary way to the thermal flux.
A process for producing semiconductor devices of planar diode type, with a very low thermal resistance, starting from a wafer consisting of a substrate, at least one active layer of semiconductor material exhibiting electrodes and a metal coating, said process comprising the following steps:
A process for producing semiconductor devices of mesa diode type with a very low thermal resistance, starting from a wafer consisting of a substrate supporting mesa diode structures protected by a passivation layer except at the tops of the mesa structures whereon a metallic coating is deposited, said process comprising the following steps:
A process for producing semiconductor devices of transistor type, with a very low thermal resistance, starting from a transistor device comprising a substrate, interleaved emitter and base regions and finger shaped metallisations in contact with said regions and leading respectively to a common emitter stump and to a common base stump, said process comprising the following steps:
Dependencies are inferred from the claim text.