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US 4,140,930 AGranted
Voltage detection circuit composed of at least two MOS transistors
AssigneeSharp Kabushiki Kaisha
InventorShinichi Tanaka
Life of this patent
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Abstract
A voltage level detection circuit comprises a first MOS transistor having the gate and the drain connected together with a power source voltage V.sub.DD via a resistor and the source grounded and a second MOS transistor having the gate connected with the drain of the first MOS transistor and the source grounded via a resistor. The circuit functions to compare the power source voltage V.sub.DD with a sum of the threshold voltage levels of the first and second MOS transistors, whereby voltage detection outputs are developed at the source of the second MOS transistor.
Claims7
A voltage level detection and switching circuit comprising:
- a first MOS transistor;
- a second MOS transistor;
- a power source providing a source voltage;
- means for comparing the source voltage with the sum of the threshold voltage levels of said first and second MOS transistors;
- a flip-flop coupled to said comparison means, the output of said flip-flop being utilized as an initial condition setting signal;
- means for setting or resetting said flip-flop when the power source voltage exceeds the sum of the threshold voltage levels of said first and second MOS transistors.
3 more elements
Dependencies are inferred from the claim text.