Stereo demodulator system
AssigneeSony Corporation
InventorMitsuo Ohsawa
Life of this patent
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Abstract
A stereo demodulator system includes first and second differential amplifiers differentially responding to a first form of a stereo signal and at least a pair of differentially connected transistors serially connected to the output circuit of the first differential amplifier and responding to a second signal related to the first signal. A current mirror circuit is provided from the output circuit of the second differential amplifier to the pair of differentially connected transistors to produce a mixed output signal at the output terminal of the pair of transistors to separate the stereo signal into component signals. An offset current compensator is provided to avoid producing an offset current in the mixed output signal.
Claims14
A stereo signal demodulator comprising
- a source of DC voltage;
- a first differential amplifier including at least first and second transistors and each having a base, emitter and collector;
- a second differential amplifier including at least third and fourth transistors each having a base, emitter and collector;
- multiplier circuit means including additional transistors each having a base, emitter and collector and being connected with said first differential amplifier, said multiplier circuit means having said multiplier circuit means having respective first and second output terminals for providing a demodulated stereo signal, and in which, because of base-emitter currents in said additional transistors, an unwanted offset current appears at said output terminals;
- current mirror circuit means connected between said source and one of said collectors of said transistors of the second differential amplifier and between said source and said multiplier circuit means;
- input means for applying a composite stereo signal to said first and second differential amplifiers, and for applying a demodulating signal to said multiplier circuit means;
- and
- current compensating means interposed between said current mirror circuit means and the collector of one of said third and fourth transistors and being responsive to the collector current of one of said third and fourth transistors for adjusting the current in said current mirror circuit means in the sense to minimize said offset current.
Dependencies are inferred from the claim text.