Switching circuit
AssigneeKabushiki Kaisha Daini Seikosha
InventorKojiro Tanaka
Life of this patent
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Abstract
A switching circuit including a flip-flop which receives a switching signal that sets the flip-flop and which receives a reset signal which resets the flip-flop. A latching circuit, responsive to a clock signal, is connected to receive an output signal of the flip-flop for developing a latching circuit output signal corresponding to the output signal of the flip-flop at a time the clock signal is applied thereto. A reset signal and a clock signal developed repetitively and out of phase are respectively applied to the flip-flop and the latching circuit so that the latching circuit output signal can change only after the flip-flop has been reset.
Claims7
A switching circuit for receiving an input signal under control of a mechanical switch having chatter and for developing in response thereto a chatter-free output signal, said switching circuit comprising:
- a C-MOS inverter circuit comprised of a complementary pair of MOS transistors connected in series, each having a respective gate for receiving a reset signal, and said complementary pair of MOS transistors having an output terminal for developing an inverter output signal thereat;
- a mechanical switch connected in series with said series-connected complementary transistor pair and having an open and a closed condition for applying an electrical signal under control of said mechanical switch to said series-connected complementary transistor pair, wherein said inverter circuit developes the inverter output signal when said mechanical switch is closed only in the absence of the reset signal;
- a flip-flop circuit connected to receive the inverter output signal as an input signal, and having an output terminal for developing thereat a flip-flop output signal determined by the inverter output signal applied to said flip-flop circuit;
- latching circuit means responsive to a clock signal longer than the reset signal and connected to receive the flip-flop output signal for developing said chatter-free output signal corresponding to the flip-flop output signal at a time the clock signal is applied to said latching circuit means;
- and
- means for developing said clock signal and said reset signal repetitively and out of phase and for applying the reset signal to said inverter circuit and for applying the clock signal to said latching circuit means, respectively, whereby said chatter-free output signal can change only after said inverter circuit receives the reset signal.
A switching circuit for receiving an input signal under control of a mechanical switch having chatter and for developing in response thereto a chatter-free output signal, said switching circuit comprising:
- a two-input NOR gate having a first input terminal for receiving in use a clock pulse signal;
- an inverter circuit having an input terminal connected to an output terminal of said NOR gate and having an output terminal for developing an inverter output signal thereat connected to the second input terminal of said NOR gate;
- a mechanical switch connected to both the input terminal of said inverter circuit and said output terminal of said NOR gate for applying an electrical signal thereto under control of said mechanical switch;
- and
- memory means connected to receive the inverter output signal for developing in response thereto the chatter-free output signal of the switching circuit.
Dependencies are inferred from the claim text.