Direct memory access module for a controller

A computerized controller having direct memory access data capability for directing control registers of a host machine comprising:

• (a) microprocessor means for manipulating data according to a given program, and for providing the manipulated data and enabling addresses;
• (b) system bus means operative to normally be under the control of said microprocessor means for bidirectionally carrying said manipulated data and enabling addresses from said microprocessor means;
• (c) data memory means coupled to receive the manipulated data from said system bus means for storing and for writing of data that has been stored onto said system bus means;
• and
• (d) direct memory access means operative to receive a predetermined enabling address on said system bus means from said microprocessor means for issuing a hold signal to said microprocessor means for suspending operation of said microprocessor means for a predetermined time, and upon receipt of a hold acknowledgement signal from said microprocessor means for assuming control of said system bus means for outputting active state control signals and predetermined accessing addresses on said system bus means that will directly access said data memory means to obtain data that has been stored to update-refresh the control registers in the host machine, said direct memory access means including:
• (1) function decoder means operative to receive address bus signals on said system bus means from said microprocessing means for recognition of predetermined addresses, for generating signals for enabling direct memory access, and for controlling writing of said data memory means data into said system bus means;
• (2) address bus controller means operative to receive update-refresh addresses from said direct memory access means and for merging of the update-refresh addresses onto the respective address bus lines of said system bus means upon receipt of an active state control signal from said direct memory access means;
• (3) multiplexing means operative to receive multi-source data from the controller for selection of data signals as the current access by a control signal from said function decoder means, and for outputting the selected data signals onto said system bus means;
• (4) first shift register means adapted to admit the selected data signals from said multiplexing means for buffer latching for providing stabilized data upon receipt of a written control signal from said function decoder means;
• (5) tri-state driver means disposed to accept the stabilized data from said shift register means for normal flow through said system bus means, and for obstruction thereof upon receipt of an active-state control signal from said direct memory access means;
• and (6) second shift register means adapted to admit data signals on said system bus means from said microprocessor means and from said tri-state driver means for buffer latching the data signal representing the current access for stabilized data upon receipt of a write control signal from said function decoder means.

An improved computerized controller having direct memory access data capability for directing control registers of a host machine having microprocessor means for manipulating data according to a given program, and for providing manipulated data and enabling addresses;

• and system bus means operative to normally be under the control of said microprocessor means for bidirectionally carrying manipulated data and enabling addresses from said microprocessor means and data memory means coupled to receive manipulated data from said system bus means, said system bus means for storing and for writing of data that has been stored onto said system bus means, wherein the improvement comprises:
• direct memory access means operative to receive a predetermined enabling address on said system bus means from said microprocessor means for issuing a hold signal to said microprocessor means for suspension of operation of said microprocessor means for a predetermined time, and upon receipt of a hold acknowledgement signal from said microprocessor means for assuming control of said system but means for outputting active state control signals and predetermined accessing addresses on said system bus means that will direct access said data memory means to obtain data that has been stored to update-refresh the control registers in the host machine, said direct memory access means further includes:
• (1) function decoder means operative to receive address bus signals on said system bus means from said microprocessor means for recognition of predetermined addresses, for generating signals for enabling direct memory access, and for controlling writing of said data memory means data into said system bus means;
• (2) address bus controller means operative to receive update-refresh addresses from said direct memory access means and for merging of the update-refresh addresses onto the respective address bus lines of said system bus means upon receipt of an active state control signal from said direct memory access means;
• (3) multiplexing means operative to receive multisource data from the controller for selection of data signals as the current access by a control signal from said function decoder means, and for outputting the selected data signals onto said system bus means;
• (4) first shift register means adapted to admit the selected data signals from said multiplexing means for buffer latching for providing stabilized data upon receipt of a write control signal from said function decoder means;
• (5) tri-state driver means disposed to accept the stabilized data from said shift register means for normal flow through said system bus means, and for obstruction thereof upon receipt of an active-state control signal from said direct memory access means;
• and
• (6) second shift register means adapted to admit data signals on said system bus means from said microprocessor means and from said tri-state driver means for buffer latching the data signal representating the current access for stabilized data upon receipt of a write control signal from said function decoder means.