# US 4,137,463 A · Control system utilizing momentary switching devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,137,463 A - Document ID: US4137463A - Status: Granted - Kind: A - Application number: 05/807,009 - Filed: 1977-06-16 - Granted: 1979-01-30 - Earliest claimed: 1977-06-16 - Assignees: P.R. Mallory & Co. Inc. - Inventors: Charles E. Scott; James E. Small - Web page: https://patentgrep.com/patent/US4137463A ## CPC - G05B 19/07: where the program is defined in the fixed connection of electrical elements, e.g. potentiometers, counters or transistors - G05B 19/108: {characterised by physical layout of switches; switches co-operating with display; use of switches in a special way} - G05B 2219/23466: Block, latch entry keys once program launched - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) ## Abstract A control system, for a machine and the like having at least one cycle made up of at least two events, utilizes momentary switching devices to actuate each cycle. The control system includes a control circuit having momentary switching devices, digital circuitry for latching the control circuit in various modes of operation, and timing circuitry responsive to the digital circuitry for timing at least one event of the cycle; and gate circuit means controlled by semiconductor switching devices for regulating at least another event of the cycle in response to the control circuit. ## Claims ### Claim 1 A control circuit for a machine and the like having at least one cycle made up of at least one event comprising: a plurality of momentarily operable programming means for actuating said cycle and for selectively programming a plurality of time periods of said event, first gate circuit means responsive to a momentary signal provided by said programming means for latching said control circuit in at least one mode of operation, timing mens responsive to said latching of said first gate circuit means for timing said event in accordance with a selectively programmed time period, said timing means including an oscillator circuit means for generating a series of electrical pulses having a frequency variable in accordance with said selectively programmed time periods and a counter for counting a fixed number of said electrical pulses generated by said oscillator circuit means, and function control means responsive to an electrical signal provided by said timing means when said fixed number of said electrical pulses have been counted for latching said control circuit in at least another mode of operation. ### Claim 2 (depends on 1) The control circuit as recited in claim 1 wherein said function control means latches said control circuit in said other mode of operation in response to at least one output of said first gate circuit means and said counter is reset in response to a momentary signal provided by said function control means. ### Claim 3 (depends on 2) The control circuit as recited in claim 2 wherein said first gate circuit means is latched in said other mode of operation in response to said momentary signal provided by said function control means. ### Claim 4 (depends on 3) The control circuit as recited in claim 3 wherein said first gate circuit means includes a plurality of NOR gates, each of said NOR gates having a plurality of inputs and an output. ### Claim 5 (depends on 4) The control circuit as recited in claim 4 wherein some at least of said inputs of said NOR gates of said first gate circuit means are electrically coupled to said programming means such that some at least of said NOR gates of said first gate circuit means are caused to make a logical transition in response to said momentary signal from said programming means. ### Claim 6 (depends on 5) The control circuit as recited in claim 5 wherein some at least of said NOR gates of said first gate circuit means are caused to make a logical zero transition and one at least of said NOR gates of said first gate circuit means is caused to make a logical one transition. ### Claim 7 (depends on 5) The control circuit as recited in claim 5 wherein said function control means includes a second gate circuit means and a bipolar semiconductor switching device. ### Claim 8 (depends on 7) The control circuit as recited in claim 7 wherein said second gate circuit means latches in response to said momentary signal provided by said programming means and to at least one output of said NOR gates of said first gate circuit means and includes at least one NOR gate having a plurality of inputs and an output. ### Claim 9 (depends on 8) The control circuit as recited in claim 8 wherein one at least of said inputs of said NOR gate of said second gate circuit means is electrically coupled to said programming means such that said NOR gate of said second gate circuit means is caused to make a logical transition in response to said momentary signal from said programming means. ### Claim 10 (depends on 9) The control circuit as recited in claim 9 wherein said NOR gate of said second gate circuit means is caused to make a logical zero transition. ### Claim 11 (depends on 8) The control circuit as recited in claim 8 wherein said bipolar semiconductor switching device includes a PNP transistor having its base electrically coupled to an output of said counter and its collector electrically coupled to at least one input of one at least of said NOR gates of said first gate circuit means such that said NOR gate of said first gate circuit means is caused to make a logical transition when said PNP transistor is switched on. ### Claim 12 (depends on 11) The control circuit as recited in claim 11 wherein said NOR gate of said first gate circuit means is caused to make a logical one to logical zero transition. ### Claim 13 (depends on 11) The control circuit as recited in claim 11 wherein said PNP transistor is momentarily switched on when said counter has counted said fixed number of said pulses and its collector is further electrically coupled to said counter such that said counter is reset in response to said momentary switching on of said transistor. ### Claim 14 (depends on 8) The control circuit as recited in claim 8 wherein one at least of said inputs of said NOR gate of said second gate circuit means is electrically coupled to said output of one at least of said NOR gates of said first gate circuit means such that said NOR gate of said second gate circuit means is caused to make a logical transition in response to a logical transition of said NOR gate of said first gate circuit means. ### Claim 15 (depends on 14) The control circuit as recited in claim 14 wherein said NOR gate of said second gate circuit means is caused to make a logical zero to logical one transition in response to a logical zero state of said NOR gate of said first gate circuit means. ### Claim 16 (depends on 8) The control circuit as recited in claim 8 wherein said oscillator circuit includes switching means for implementing said logical transition made by said first gate circuit means. ### Claim 17 (depends on 16) The control circuit as recited in claim 16 wherein said switching means is electrically coupled to said outputs of said NOR gates of said first gate circuit means such that said timing means is switched on in response to a logical one state of one at least of said NOR gates of said first gate circuit means. ### Claim 18 (depends on 1) The control circuit as recited in claim 1 wherein said programming means include a plurality of momentarily operable switching devices. ### Claim 19 (depends on 18) The control circuit as recited in claim 18 wherein said programming means includes at most four momentarily operable switching devices. ### Claim 20 In a control circuit for controlling a machine and the like having at least one cycle made up of at least one event, a timing means for timing said event comprising: oscillator circuit means responsive to an electrical signal for deriving a plurality of time periods for said event; said oscillator circuit means including switching means for activating said oscillator circuit means, a clock responsive to said switching means for generating a series of electrical pulses, and impedance means for defining a plurality of selectable frequencies of said electrical pulses, said frequencies variable in accordance with selected time periods for said event; and a counter for counting a fixed number of said electrical pulses generated by said oscillator circuit means; said plurality of time periods substantially equivalent to various times required for said counter to count said fixed number of said electrical pulses. ### Claim 21 (depends on 20) The timing means as recited in claim 20 wherein said switching means includes a plurality of bilateral switching devices for logic implementation. ### Claim 22 (depends on 21) The timing means as recited in claim 21 wherein each of said bilateral switching devices has a unilateral input, a bilateral input, and an output. ### Claim 23 (depends on 22) The timing means as recited in claim 22 wherein said unilateral input of one at least of said bilateral switching devices is electrically coupled to said impedance means. ### Claim 24 (depends on 23) The timing means as recited in claim 23 wherein said logic is implemented through said bilateral input of said bilateral switching devices such that said impedance means is electrically coupled to said output of said bilateral switching device. ### Claim 25 (depends on 24) The timing means as recited in claim 24 wherein said impedance means include a plurality of resistance means and said output of said bilateral switching means is electrically coupled to said clock such that at least one frequency of said electrical pulses generated by said clock is defined. ### Claim 26 (depends on 25) The timing means as recited in claim 25 wherein said time periods for said event are determined by said selectable frequencies of said electrical pulses generated by said clock and said counter signals completion of a selected time period after counting said fixed number of said pulses. ### Claim 27 (depends on 26) The timing means as recited in claim 26 wherein said clock is an oscillator and said counter is a binary ripple counter. ### Claim 28 A control system for controlling a machine and the like having at least one cycle made up of at least two events comprising in combination: a power supply source; a control circuit responsive to said power supply source including momentarily operable programming means for actuating said cycle and for selectively programming a plurality of time periods of a first event, first gate circuit means responsive to a momentary signal provided by said programming means for latching said control circuit in a first mode of operation wherein said first event is activated, timing means responsive to said latching of said first gate circuit means for timing said first event of said machine in accordance with a selectively programmed time period, and function control means responsive to an electrical signal provided by said timing means after said selectively programmed time period has elapsed, said function control means including second gate circuit means for latching said control circuit in a second mode of operation wherein said first event is deactivated and a second event is activated, and third gate circuit means responsive to said latching of said function control means for regulating said second event of said machine. ### Claim 29 (depends on 28) The control system as recited in claim 28 wherein said timing means includes oscillator circuit means electrically coupled to said first gate circuit means for deriving said selectively programmed time period for said first event and a counter responsive to said oscillator means for signalling the end of said first event. ### Claim 30 (depends on 29) The control system as recited in claim 29 wherein said oscillator circuit means includes switching means for activating said oscillator circuit means, a clock responsive to said switching means for generating a series of electrical pulses, and impedance means for defining a plurality of selectable frequencies of said electrical pulses, said frequencies variable in accordance with selected time periods for said first event. ### Claim 31 (depends on 29) The control system as recited in claim 29 wherein said function control means latches said control circuit in said second mode of operation in response to said first gate circuit means and said counter is reset in response to a momentary signal provided by said function control means. ### Claim 32 (depends on 31) The control system as recited in claim 31 wherein said first gate circuit means is latched in said second mode of operation in response to said momentary signal provided by said function control means. ### Claim 33 (depends on 32) The control system as recited in claim 32 wherein said first gate circuit means includes a plurality of NOR gates, each of said NOR gates having a plurality of inputs and an output. ### Claim 34 (depends on 33) The control system as recited in claim 33 wherein said second gate circuit means latches in said first mode of operation in response to said momentary signal provided by said programming means and latches in said second mode of operation in response to an output of at least one of said NOR gates of said first gate circuit means and includes at least one NOR gate having a plurality of inputs and an output. ### Claim 35 (depends on 28) The control system as recited in claim 28 further including switching means electrically coupled to said third gate circuit means and to said first event for administering a sequential activation and deactivation of said first and second events. ### Claim 36 (depends on 35) The control system as recited in claim 35 wherein said first event is activated in response to a logical zero state of said second gate circuit means and said first event is deactivated in response to a logical one state of said second gate circuit means. ### Claim 37 (depends on 36) The control system as recited in claim 36 wherein said second event is activated and deactivated in response to said logical one state of said second gate circuit. ### Claim 38 (depends on 37) The control system as recited in claim 37 wherein said third gate circuit means includes at least one NOR gate having at least two inputs and an output and delay timing means responsive to said output of said second gate circuit means for timing said second event. ### Claim 39 (depends on 38) The control system as recited in claim 38 wherein said NOR gate of said third gate circuit means is caused to make a logical one transition in response to said logical zero state of said second gate circuit means. ### Claim 40 (depends on 39) The control system as recited in claim 39 wherein said delay timing means is electrically coupled to said NOR gate of said third gate circuit means such that a logical one to logical zero transition of said NOR gate which occurs in response to a change in logical state of said second gate circuit means is delayed for a predetermined time representing a time period of said second event. ### Claim 41 (depends on 40) The control system as recited in claim 40 wherein said switching means includes a bidirectional semiconductor switching device for activating and deactivating said first event and for activating said second event.