Apparatus for performing floating point arithmetic operations using submultiple storage

An apparatus for multiplying a multiplicand by the selection of submultiples of said multiplicand in accordance with the bits of a multiplier, said apparatus comprising:

• a number of multibit processor chips connected to operate in tandum each chip having a number of terminals and including:
• an arithmetic logic unit section;
• a multibit addressable random access memory section connected to said arithmetic logic unit section, each said memory section having a plurality of multibit storage locations, a group of said locations storing a number of different predetermined submultiple digits of said multiplicand having values selected to have a predetermined relationship to the values of bits of said multiplier used in selecting said submultiples and another location for storing a partial product value;
• a multibit position shift register section for storing said multiplier, coupled to said arithmetic and logic unit section, a most significant bit position and a least significant bit position of each said multibit position shift register section connected to first and second ones of said number of terminals;
• and,
• a multibit input shift section connected to said memory section, to said arithmetic logic unit section and to third and fourth ones of said number of terminals;
• first conductor means connecting said second terminal of different ones of said chips to the first terminal of an alternate succeeding chip so as to enable a multidigit shifting of the multiplier digit contents of said shift register sections during a cycle of operation;
• second conductor means connecting said third and fourth terminals of each chip to said fourth and said third terminals respectively of a next succeeding and the preceding one of said chips for enabling the shifting by one bit position signals to be stored in said memory section;
• submultiple selection circuit means having a number of input terminals connected to receive selection signals from a number of said second terminals of predetermined ones of said number of chips storing a group of successive multiplier digits and output terminals connected to each said addressable random access memory section, said selection signals conditioning each of said memory sections for read out of the digits of a next submultiple of said multiplicand upon the shifting of said multiplier digit contents of said shift register sections in a predetermined direction by one bit position for summing to said partial product value stored in said another location of said memory sections by said arithmetic and logic sections for producing an output partial product generated from simultaneously processing several bits of said multiplier during said cycle of operation and each of said multibit input shift sections shifting said digits of said output partial product by one bit position during said cycle of operation before storage in said another location for a next cycle of operation.

An apparatus for multiplying a multiplicand by the selection of submultiples of said multiplicand in accordance with the bits of a multiplier, said apparatus comprising:

• a number of multibit microprocessor chips connected to operate in tandum, each chip having a number of terminals and including:
• an arithmetic logic unit section having first and second sets of input terminals for receiving first and second operands respectively;
• a multibit addressable random access memory section connected to said arithmetic logic unit section, each said memory section having a plurality of digit storage locations, a group of said locations storing a number of different predetermined digits of submultiples of said multiplicand having values selected to have a predetermined relationship to the values of bits of said multiplier used in selecting said submultiples and another location for storing a partial product value;
• a multibit position shift register section for storing said multiplier, a most significant bit position and a least significant bit position of each said multibit position shift register section connected to first and second ones of said number of terminals;
• a multibit random access memory shift and multiplexer section connected to said random access memory section and to third and fourth ones of said number of terminals;
• and,
• an input multiplexer section connected to said arithmetic logic unit section, to said shift register section and to said first and second ones of said number of terminals;
• first conductor means connecting said second terminal of different ones of said chips to the first terminal of an alternate third chip so as to enable multidigit shifting of the multiplier digit contents of said shift register sections during a cycle of operation;
• submultiple selection circuit means having a number of input terminals connected to receive selection signals from a number of said second terminals of predetermined ones of said number of chips storing a group of successive multiplier digits and output terminals connected to each said addressable random access memory section, said selection signals conditioning each of said memory sections for read out of the digits of a next submultiple of said multiplicand to said first set of input terminals of said arithmetic logic unit section upon the shifting of said multiplier digit contents of said shift register sections in a predetermined direction by one bit position by said input multiplexer section for summing to said partial product value read out from said another location of said memory sections to said second set of input terminals of said arithmetic logic unit section by said arithmetic and logic sections for producing an output partial product generated from simultaneously processing several bits of said multiplier during said cycle of operation and each of said multibit random access memory shift and multiplexer sections shifting said digits of said output partial product by one bit position during said cycle of operation before storage in said another location for a next cycle of operation.