US 4,128,890 A · Integrated arithmetic unit and digital networks using the unit

Abstract

The invention relates to an arithmetic unit fabricated by large scale integration techniques and to an improved digital network of increased accuracy in which the unit finds application. The integrated circuit comprises an initial summing means, rounding means, full precision multiplication logic and three successive summing means, all elements being successively connected, and all except the first having both internal and external input terminals. The unit is flexible in respect to the length of the operands and their sign notation. The terminals are readily cascaded, permitting interconnection of the unit with like integrated circuit units and with external delay elements. The invention is applicable in a variety of complex operations including digital filtering, correlation, convolution, polynomial evaluation and squaring. In many of these applications, mixed precision and rounding provide increased accuracy in the resulting digital networks.

Claims21

Dependent claims

An integrated arithmetic unit for use in a serial digital network comprising:

A. a first summer for signed serial data having a pair of inputs (D1, D2) for external connection and producing an output sum in signed serial format;
(D1 + D2)
B. four quadrant multiplication logic for signed serial data having a first input coupled to the output of said summer, a second input (X) for external connection, said multiplication logic producing a double precision output product in signed serial format;
(D1 + D2) X
and
C. a second summer for signed serial data having a first input coupled to the output of said multiplication logic, a second input (S1) for external connection, and producing an external output sum (O1) in signed serial format:
O1 = [(D1 + D2) X + S1].

4 more elements

A digital network comprising:

A. a first serial summer having a pair of signed inputs for producing an algebraic sum,
B. rounding means coupled to the output of said summer for rounding to an m bit word length,
C. serial four quadrant multiplication logic having a first m bit multiplicand input coupled to the output of said rounding means and a second n bit multiplier input (X), said multiplication logic producing a double precision output product in words of m + n bits,
D. a second serial summer having a first signed input coupled to the output of said multiplication logic, and a second signed input, and producing an algebraic output sum, said network having a predetermined transport delay (D) between the input to said first serial summer and the output of said second serial summer,
E. a first delay element connected in a feedback path for coupling data between the output of said second summer and an input of said first summer and having a delay (.DELTA.) substantially equal to the difference in bit times between (m + n) and D, to combine the output data with the data in said other input of said first summer during the succeeding word, and
F. a second delay element coupled between the output of said first delay element and said second input (S1) to said second summer, having a delay substantially equal to said transport delay (D), so that the output data is coupled to the data applied to the first input of said second summer during the succeeding word to form a double precision feedback loop.

3 more elements

Dependencies are inferred from the claim text.

Integrated arithmetic unit and digital networks using the unit

Life of this patent

Integrated arithmetic unit and digital networks using the unit

Life of this patent

Abstract

Claims21