Reading capacitor memories with a variable voltage ramp

The process of reading a metal-nitride-oxide-silicon capacitor memory array having a plurality of digit lines and a plurality of word lines, and said memory including a plurality of cells, each cell having a plurality of charge states, including the steps of

• applying a variable potential across the word line and digit line identifying a selected cell, said variable potential extending at least in part across a "flat-band" portion of a known voltage-capacitance relationship for said cell, the magnitude of said variable potential being sufficiently small so that a charge stored in said selected cell is not substantially changed,
• biasing substantially all unselected cells into a depletion state,
• measuring the current flowing through said selected capacitor cell as a function of said voltage versus time, and
• determining the state of said capacitor cell by the shape of the current versus time profile.

The process of reading a metal-nitride-oxide-silicon capacitor memory array having a plurality of digit lines and a plurality of word lines, said memory including a plurality of cells, each cell having a plurality of charge states, including the steps of

• applying a variable voltage ramp potential across the word and digit line identifying a selected cell, said variable potential extending at least in part across a "flat-band" portion of a known voltage-capacitance relationship for said cell, the magnitude of said variable potential being sufficiently small so that a charge stored in said selected cell is not substantially changed,
• placing a resistor in a series connection with said selected cell,
• biasing substantially all unselected cells connected to said resistor through said lines into a depletion state,
• measuring the current flowing through said selected capacitor cell as a function of said voltage versus time by measuring a voltage drop across said resistor,
• measuring a change of said voltage drop versus time, and
• determining from any amplitude jumps in said voltage drop signal the state of the capacitor being read.

The process of reading a selected cell of a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of digit lines, one each of said digit and word lines uniquely identifying a capacitor cell, and each cell hving two capacitance states, the process including the steps of

• applying a variable voltage ramp potential across the word and digit line identifying a selected cell, said variable potential extending at least in part across a "flat-band" portion of a known voltage-capacitance relationship for said cell, the magnitude of said variable potential being sufficiently small so that a charge stored in said selected cell is not changed,
• placing a resistor in a series connection with said selected cell,
• biasing substantially all unselected cells connected to said resistor through said lines into a depletion state,
• measuring the current flowing through said selected capacitor cell as a function of said voltage versus time, and
• determining the state of the capacitor cell from the shape of the voltage versus time profile.