Dual port random access memory storage cell

A dual port memory cell comprising:

• (a) a first storage cell including first and second cross-coupled transistors,
• (b) first selection means coupled to said first storage cell for selecting said first storage cell,
• (c) a second storage cell including third and fourth cross-coupled transistors,
• (d) second selection means coupled to said second storage cell for selecting said second storage cell, and
• (e) coupling means responsive to said first and second selection means for coupling said first storage cell to said second storage cell and for causing a state stored in a selected one of said storage cells to be also stored in an unselected other of said storage cells, said coupling means including first, second, third, and fourth coupling transistors, said first and second coupling transistor each having its base coupled to the base of said first and second cross-coupled transistor, respectively, and its emitter coupled to the base of said third and fourth cross-coupled transistor, respectively, and said third and fourth coupling transistor each having its base coupled to the base of said third and fourth cross-coupled transistor, respectively, and its emitter coupled to the base of said first and second cross-coupled transistors, respectively.

A dual port memory cell comprising:

• (a) a first storage cell including first and second cross-coupled transistors,
• (b) first selection means coupled to said first storage cell for selecting said first storage cell,
• (c) a second storage cell including third and fourth cross-coupled transistors,
• (d) second selection means coupled to said second storage cell for selecting said second storage cell, and
• (e) coupling means responsive to said first and second selection means for coupling said first storage cell to said second storage cell and for causing a state stored in a selected one of said storage cells to be also stored in an unselected other of said storage cell, said coupling means including a first pair of reverse parallel coupled diodes coupled between the collectors of said first and third cross-coupled transistors and also including a second pair of reverse parallel coupled diodes coupled between the collectors of said second and fourth cross-coupled transistors.

A dual port memory circuit for storing digital data comprising:

• (a) a plurality of memory cells, each of said memory cells including switching transistor means for storing a binary logic state,
• (b) first write-sense means coupled to said plurality of memory cells for writing digital data into said sensing digital data from each of said plurality of memory cells,
• (c) second write-sense means coupled to said plurality of memory cells for writing digital data into and sensing digital data from each of said plurality of memory cells, and
• (d) said first and second write-sense means being simultaneously operative for writing signal data into and sensing digital data from said plurality of memory cells.

A dual port memory circuit for storing digital data comprising:

• (a) a plurality of memory cells, each of said plurality of memory cells including a first and second storage cell and including coupling means for coupling said first storage cell to said second storage cell and for providing a transfer of digital data between said first and second storage cells,
• (b) first write-sense means coupled to said plurality of memory cells for writing digital data into and sensing digital data from any one of said plurality of memory cells,
• (c) second write-sense means coupled to said plurality of memory cells for writing digital data into and sensing digital data from any one of said plurality of memory cells, and
• (d) first and second write-sense means being simultaneously operative for writing digital data into and sensing digital data from said plurality of memory cells.